3f8f726296
make rocc build independent from parameter structure
2015-12-01 18:47:52 -08:00
dcca0b1d86
fix up FPU connection
2015-12-01 18:14:58 -08:00
08f77ca90d
Merge branch 'master' into rocc-fpu-port
2015-12-01 18:00:28 -08:00
cdc476a370
change Rocc parameterization
2015-12-01 17:56:09 -08:00
e76dfa55f7
change the way rocc is parameterized
2015-12-01 17:54:56 -08:00
e0d849fec5
Fix zscale testing
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Use the following command in vsim:
make CONFIG=ZscaleConfig MODEL=ZscaleTop TB=ZscaleTestHarness run-asm-tests
2015-12-01 17:31:48 -08:00
4833d41dbc
make the connection of FPU ports optional per accelerator
2015-12-01 16:48:05 -08:00
5eeb8969f6
fix zscale build (run still fails)
2015-12-01 16:20:34 -08:00
c8c68e75bb
base NGenerators on NTiles, not the other way around
2015-12-01 15:26:09 -08:00
0b15b19381
add arbiter for FPU
2015-12-01 10:22:31 -08:00
1db2da00f3
Merge branch 'master' into rocc-fpu-port
2015-11-30 19:18:58 -08:00
e4043570bd
bump groundtest and hardfloat
2015-11-30 18:06:15 -08:00
40d68406d6
use xlen parameter for ALU
2015-11-30 18:04:44 -08:00
e80340198a
use implicit parameters for ALU
2015-11-30 17:35:33 -08:00
ec4ade988b
[travis] add multiple configs including rocc
2015-11-28 07:17:49 -08:00
7259239ba4
Merge pull request #31 from ucb-bar/multirocc
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implement support for multiple RoCC accelerators
2015-11-28 08:56:07 -05:00
90991014a0
Merge pull request #19 from ucb-bar/multirocc
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Add support for multiple RoCC accelerators
2015-11-28 08:56:04 -05:00
7083576156
fix typo in NastiErrorSlave
2015-11-26 12:57:04 -08:00
23f0756978
implement support for multiple RoCC accelerators
2015-11-26 12:49:04 -08:00
9256239206
implement support for multiple RoCC accelerators
2015-11-26 12:46:01 -08:00
58b0a86834
some modifications to AccumulatorExample
2015-11-26 08:48:19 -08:00
e25a020e60
Construct device tree ROM in MMIO region
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Rebuild riscv-tools for this to work!
2015-11-25 21:23:37 -08:00
e52685f2e9
Fix LoadGen zero flag
2015-11-25 20:52:30 -08:00
27df04354f
Add ROM with NASTI interface
2015-11-25 20:04:31 -08:00
49d93da87e
Factor out more common zscale code
2015-11-24 19:17:21 -08:00
e203b8b378
Make ALU generic for zscale
2015-11-24 19:17:07 -08:00
52b25c3da0
Factor out more common zscale code
2015-11-24 18:34:03 -08:00
5294e94794
Remove CSR back pressure ability
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We were using it for IPIs, but no longer need it.
2015-11-24 18:28:14 -08:00
4616db4695
Make RegFile/ImmGen usable by zscale
2015-11-24 18:27:07 -08:00
1761db3272
Factor out some common code from zscale
2015-11-24 18:14:06 -08:00
6d1bf5c014
Use generic LoadGen/StoreGen
2015-11-24 18:13:33 -08:00
57e82442a1
Make LoadGen and StoreGen generic
2015-11-24 18:12:42 -08:00
ec6bfde9a3
fix WritebackUnit issue in uncore
2015-11-21 16:11:22 -08:00
ee6514e4f4
make sure WritebackUnit sends correct probe addresses
2015-11-21 15:55:11 -08:00
04383a31f5
Revert "make sure L2MetadataArray assigns unoccupied way if available"
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This reverts commit 1857f36c1e6f2b2859c724eea6ae3cfb2618f81b.
2015-11-21 10:35:40 -08:00
158d1d870c
do all the writes before doing the gets in GeneratorTest
2015-11-21 09:42:00 -08:00
65632c875a
Merge branch 'master' into rocc-fpu-port
2015-11-21 02:24:38 -08:00
9d50f37289
fix unused set issue for multiple L2 cache banks
2015-11-20 23:26:28 -08:00
3c95afebc6
Shift set index for multi-bank configurations
...
Prior to this commit, the L2 cache banks used the lower bits of the
block address as the set index. However, the lower bits are also used to
route addresses to different banks. As a result, in multi-bank
configurations, only a fraction of the sets in each bank could be
accessed. This commit fixes that problem by using the bits ahead of the
bank index as the set index, so that all sets in the cache can be
accessed.
2015-11-20 23:24:57 -08:00
55a85cc67a
make sure wmask is passed for PutBlock in broadcast hub
2015-11-20 14:09:24 -08:00
941b64cd62
make partial write-masking PutBlock constructor always set alloc bit
2015-11-20 13:34:07 -08:00
b0a06a77db
fix a few Chisel3 compat issues
2015-11-20 13:33:15 -08:00
ad3b7fd0e1
adjust CacheFillTest configuration
2015-11-19 10:52:14 -08:00
24f7b9f472
make sure L2MetadataArray assigns unoccupied way if available
2015-11-19 10:45:54 -08:00
4806f72b08
add CacheFillTest to check L2 conflict misses
2015-11-19 00:16:28 -08:00
49c6b1ad1c
add CacheFillTest
2015-11-19 00:15:36 -08:00
640544ea5a
generalize test harness
2015-11-18 22:54:05 -08:00
f325874420
make sure timeout doesn't trigger spuriously on reset
2015-11-18 22:53:50 -08:00
3514b6eb87
add some more useful configurations
2015-11-18 22:11:17 -08:00
379d43d5f4
make MultiChannel routing more performant
2015-11-18 22:11:17 -08:00
