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Author SHA1 Message Date
Wesley W. TerpstraandGitHub abe344a1a4 tilelink2 Fuzzer: support read-only mode (#555) 2017-02-13 00:18:47 +01:00
Wesley W. TerpstraandGitHub 69f4c1a144 AddressDecoder: support AddressSets with infinite bits (#547) 2017-02-04 15:59:50 -08:00
Wesley W. TerpstraandGitHub 71f2445c62 Merge pull request #546 from ucb-bar/dev-zero 
Dev zero
 2017-02-03 19:49:56 -08:00
Wesley W. Terpstra d1744a5667 coreplex: zero memory channels is also allowed 2017-02-03 19:00:08 -08:00
Wesley W. Terpstra a3e56cfa5e rocketchip: add Zero device to the memory subsystem 2017-02-03 17:19:24 -08:00
Wesley W. Terpstra b240505a15 rocketchip: move memory channel Xbar from coreplex to rocketchip 
We want to keep the banks split in the outer SoC if there is an L3.
Furthermore, each channel might go to different memory subsystems,
like DDR/HMC/Zero, from rocketchip.
 2017-02-03 17:19:21 -08:00
Wesley W. Terpstra fc9ea62d38 HeterogeneousBag: a handy container for differently parameterized bundles 2017-02-03 16:21:33 -08:00
Wesley W. Terpstra 7afe383db3 Ecc: detect uncorrectable errors also for SEC 2017-02-03 16:21:09 -08:00
Wesley W. Terpstra 7aba066e67 tilelink2: add TLZero; /dev/zero suitable for putting behind locked cache ways 2017-02-03 16:20:27 -08:00
Wesley W. TerpstraandGitHub 93b2fa197e Artefact output (#545) 
* build: stop using empty .prm file

* generator: general-purpose mechanism for creating elaboration artefacts
 2017-02-02 19:24:55 -08:00
Wesley W. TerpstraandGitHub b2ee5e7d38 Merge pull request #540 from ucb-bar/dedup 
Dedup rocket
 2017-01-31 17:16:43 -08:00
Wesley W. Terpstra 9ca8f514c0 rocket: creating Bundles in an object also break dedup! 2017-01-31 14:45:11 -08:00
Wesley W. Terpstra e1577bb06e chisel3: bump chisel3 for work deduplication 2017-01-31 14:20:07 -08:00
Wesley W. Terpstra e5af59db68 rocketchip: work-around ucb-bar/chisel3#472 2017-01-31 14:20:02 -08:00
Wesley W. TerpstraandGitHub 9c0cc6fdf4 Merge pull request #537 from ucb-bar/l2-banks-together 
BankedL2Config: use the same LazyModule for all L2 banks
 2017-01-30 15:39:04 -08:00
Wesley W. Terpstra dc66c8857f diplomacy: be more robust using Java introspection 
If an error occures, some objects might only be partially initialized.
We want to still be able to get nice names for error messages.
 2017-01-30 14:25:12 -08:00
Wesley W. Terpstra 280af9684b BankedL2Config: use the same LazyModule for all L2 banks 
This makes it much easier for banked coherence managers to support
cross-bank functionality, like a common control port, for example.
 2017-01-30 14:02:59 -08:00
Wesley W. Terpstra f7f52cc722 diplomacy: restore Monitor functionality 2017-01-29 17:25:14 -08:00
Wesley W. Terpstra 972953868c uncore: switch to new diplomacy Node API 
Most adapters should work on multiple ports.
This patch changes them all.
 2017-01-29 15:54:45 -08:00
Wesley W. Terpstra 4d646939b0 diplomacy: make flexible-port adapters possible 2017-01-29 14:26:02 -08:00
Wesley W. Terpstra 24ee7f45f5 rocketchip: pass variable l1tol2 connections into coreplex 2017-01-29 11:18:36 -08:00
Wesley W. Terpstra d5fa159063 diplomacy: add :*= and :=* to support flexible # of edges 2017-01-28 21:32:36 -08:00
Wesley W. TerpstraandGitHub 03f2fe02ac coreplex: support rational crossing to L2 (#534) 2017-01-27 17:09:43 -08:00
Wesley W. TerpstraandGitHub 19c58630d2 Merge pull request #533 from ucb-bar/rational-crossing 
Rational clock crossing
 2017-01-26 22:30:04 -08:00
Wesley W. Terpstra 830d01329d RationalCrossing: add some documentation 2017-01-26 21:27:34 -08:00
Wesley W. Terpstra fc3b72084f tilelink2: add a rational clock crossing adapter 2017-01-26 20:07:28 -08:00
Wesley W. Terpstra 4b70386393 AsyncCrossing: disambiguate the file name 2017-01-26 20:07:28 -08:00
Wesley W. Terpstra 5cf4b0632d RationalCrossing: clock crossing between related clock domains 2017-01-26 20:07:28 -08:00
Wesley W. TerpstraandGitHub d1dedd25e7 Merge pull request #529 from ucb-bar/physical-optimization 
Physical optimization
 2017-01-24 18:59:07 -08:00
Wesley W. Terpstra 6ff35a387a tilelink2: disable A=>D bypass in ToAXI4 whenever possible 2017-01-24 18:11:00 -08:00
Wesley W. Terpstra 64e1de751d axi4: add a minLatency parameter 2017-01-24 18:11:00 -08:00
Wesley W. TerpstraandGitHub 46cdfc2b45 diplomacy: find names of LazyModules also in Seq() member values (#527) 2017-01-24 18:10:37 -08:00
Wesley W. TerpstraandHenry Cook 3fc55298ef coreplex: provide coherence managers with geometry information 2017-01-23 15:50:39 -08:00
Wesley W. TerpstraandHenry Cook d4b3a0f0be diplomacy: support given bits in AddressDecoder 2017-01-23 15:50:39 -08:00
Wesley W. TerpstraandHenry Cook c0b6d31377 tilelink2: Delayer adapter useful for unit tests 2017-01-23 15:50:39 -08:00
Wesley W. TerpstraandGitHub b3ef146805 Merge pull request #523 from ucb-bar/buffer-move 
coreplex: move TLBuffers for L2 and socBus
 2017-01-21 14:53:51 -08:00
Wesley W. Terpstra 38c9ddffcc BankedL2: move TLFilter BEFORE coherence manager 
This lets smart caches exclude the sets that are filtered.
 2017-01-21 13:23:07 -08:00
Wesley W. Terpstra dcadd5a006 coreplex: move TLBuffers for L2 and socBus 2017-01-20 22:23:36 -08:00
Wesley W. TerpstraandGitHub e8ce32a156 Merge pull request #515 from ucb-bar/cache-cork 
Cache cork
 2017-01-19 20:00:51 -08:00
Wesley W. Terpstra 9dc7f180b6 diplomacy: support zero-port Nodes 2017-01-19 19:08:01 -08:00
Wesley W. Terpstra c0496fab29 regression: disable build that times out on Travis 2017-01-19 19:07:59 -08:00
Wesley W. Terpstra 5d70265e86 rocket: L1 only needs cache-line transfer sizes 2017-01-19 19:07:14 -08:00
Wesley W. Terpstra 3a5e5a65f8 coreplex: support multiple memory channels via diplomatic trickery 2017-01-19 19:07:14 -08:00
Wesley W. Terpstra e7b35b4bb6 diplomacy: support multiple ports behind a BlindNode 2017-01-19 19:07:14 -08:00
Wesley W. Terpstra 258abc5629 coreplex: re-enable stateless L2 config 2017-01-19 19:07:14 -08:00
Wesley W. Terpstra 4bdb2e5d68 tilelink2 Monitor: ReleaseAck source does not count 2017-01-19 19:07:14 -08:00
Wesley W. Terpstra fbf1073586 tilelink2: CacheCork - terminate caching 2017-01-19 19:07:14 -08:00
Wesley W. Terpstra bf7823f1c8 tilelink2: split suportsAcquire into T and B variants 2017-01-19 19:07:13 -08:00
Wesley W. TerpstraandHenry Cook 52bb6cd9d9 Configs: use a uniform syntax without Match exceptions (#507) 
* Configs: use a uniform syntax without Match exceptions

The old style of specifying Configs used total functions.  The only way to
indicate that a key was not matched was to throw an exception.  Not only was
this a performance concern, but it also caused confusing error messages
whenever you had a match failure from a lookup within a lookup.  The
exception could get handled by an outer-lookup that then reported the wrong
key as missing.
 2017-01-13 14:41:19 -08:00
Wesley W. TerpstraandGitHub 4471e0de27 Merge pull request #494 from ucb-bar/diplomatic-apb 
Diplomatic apb
 2016-12-15 17:45:20 -08:00
Wesley W. Terpstra a9b264e582 ahb: lower hsel when idle to save power 2016-12-15 15:32:30 -08:00
Wesley W. Terpstra 16febe7e94 apb: add a TileLink to APB bridge and unittest it 2016-12-15 15:32:27 -08:00
Wesley W. Terpstra ed091f55e6 apb: diplomatic APB framework 2016-12-15 13:48:50 -08:00
Wesley W. TerpstraandGitHub 4d87d07343 Merge pull request #491 from ucb-bar/ahb-hready-high 
ahb: don't violate spec with SRAM fuzzing
 2016-12-15 02:50:15 +00:00
Wesley W. Terpstra a5b8fc2317 RegisterRouterTest: start up with 0 in registers to make VIP testing easier 2016-12-14 15:38:08 -08:00
Wesley W. Terpstra 9d50704b64 ahb: don't violate spec with SRAM fuzzing 2016-12-14 15:18:41 -08:00
Wesley W. TerpstraandHenry Cook 09afbbafdb ahb: weaken RegisterRouter assertion 
As written I think it could potentially fail, but what I actually care
about is something weaker that should be true. Assert: nothing lost.
 2016-12-08 18:00:39 -08:00
Wesley W. TerpstraandHenry Cook 588b944ed4 ahb: implement and test address decoding 2016-12-08 18:00:39 -08:00
Wesley W. TerpstraandHenry Cook 5d1064fcb1 ahb: include a unit test 2016-12-08 18:00:39 -08:00
Wesley W. TerpstraandHenry Cook 51dfb9cb06 ahb: TileLink master 2016-12-08 18:00:39 -08:00
Wesley W. TerpstraandHenry Cook 01b0f6a52b ahb: new diplomacy-based AHB bus definition 2016-12-08 18:00:39 -08:00
Wesley W. TerpstraandGitHub 1bd8a2e239 Merge pull request #478 from ucb-bar/parameterize-diplomatic-connections 
Parameterize diplomatic connections
 2016-12-07 15:03:53 -08:00
Wesley W. Terpstra c2eedbfe23 tilelink2 Monitor: use Parameters instead of global variables 2016-12-07 12:24:03 -08:00
Wesley W. Terpstra 020fbe8be9 diplomacy: make config.Parameters available in bundle connect() 
This makes it posisble to use Parameters to control Monitors.
However, we need to make all LazyModules carry Parameters.
 2016-12-07 12:24:01 -08:00
Wesley W. TerpstraandHenry Cook fbfa15efea TLBroadcast: support non-FIFO devices (#482) 2016-12-05 22:10:37 -08:00
Wesley W. TerpstraandGitHub 3c9718ec8f clint: undefined registers must be zero (#480) 
This is needed so that SMP-safe boot loaders can safely
read/write to the IPI register of non-existent harts.
 2016-12-05 17:11:53 -08:00
Wesley W. Terpstra b7963eca4e copyright: ran scripts/modify-copyright 2016-11-27 22:15:43 -08:00
Wesley W. Terpstra d4708694ea scripts/authors: Matthew Naylor's submissions were under Berkeley terms 2016-11-27 22:15:43 -08:00
Wesley W. Terpstra e2ec1d00ad copyright: normalize /// to // in comments 2016-11-27 22:15:43 -08:00
Wesley W. Terpstra a0e10aec05 uncore: removed obsolete Builder file 2016-11-27 22:15:43 -08:00
Wesley W. Terpstra 8510d9e697 scripts: two scripts to determine copyright holder of files 2016-11-27 22:15:38 -08:00
Wesley W. TerpstraandGitHub 4146f6a792 TLB: do not access illegal addresses (#460) 2016-11-26 15:11:42 -08:00
Wesley W. TerpstraandGitHub a17753983a coreplex: allow legacy devices to override the config string (#458) 2016-11-25 19:38:24 -08:00
Wesley W. TerpstraandGitHub 9433da8458 Merge pull request #457 from ucb-bar/jtag-depth-1 
Jtag depth 1
 2016-11-25 18:41:39 -08:00
Wesley W. Terpstra 233280e7d2 AsyncBundle: save a wasted bit when depth=1 2016-11-25 18:11:01 -08:00
Wesley W. Terpstra d755edffcc DebugTransport: use ToAsyncDebugBus for correct depth 2016-11-25 18:10:28 -08:00
Wesley W. TerpstraandGitHub 2b80386a9e rocketchip: TileInterrupts needs a TLCacheEdge (#456) 2016-11-25 17:02:29 -08:00
Wesley W. TerpstraandGitHub 1e0aca7358 dcache: the high bit of s2_req.typ is the SIGN bit (not size) (#455) 2016-11-25 15:26:22 -08:00
Wesley W. TerpstraandAndrew Waterman 0baa1c9a45 coreplex: CacheBlockOffsetBits was wrong! 
This bug is ancient. I don't understand how it never mattered before.
Anyway, in processors with a custom CacheBlockBytes, this value is wrong!
The symptom is that TL1 components end up missing high address bits.
This causes, for example, a system to jump to 0 instead of RAM.

I don't understand how this very serious bug did not cause problems before.
 2016-11-24 18:32:44 -08:00
Wesley W. Terpstra 6aeadc4551 regression: disable ComparatorL2Config for now 
This tests atomics against the L2.  However, we don't have an L2 yet so this
is hitting the broadcast hub, which does not support these operations.
 2016-11-23 20:53:36 -08:00
Wesley W. Terpstra a670f63c81 periphery: a handy trait to turn-off ExtMem 2016-11-23 20:44:45 -08:00
Wesley W. Terpstra 30e890b480 diplomacy: include InternalNodes for AXI4 and TL 2016-11-23 20:44:45 -08:00
Wesley W. Terpstra 9f1c668c4f config: when modifying Parameters, subordinate lookups use top 2016-11-23 20:44:45 -08:00
Wesley W. Terpstra 566cc9e60b rocketchip: RTCPeriod config 2016-11-23 20:44:45 -08:00
Wesley W. Terpstra e87f54d4f7 rocketchip: traits for adding external TL2 ports 2016-11-23 20:44:42 -08:00
Wesley W. Terpstra 4b9dc78951 rocketchip: add a parameter-controlled debug port 2016-11-23 15:35:53 -08:00
Wesley W. Terpstra cf8ecbd53b travis: balance regression tasks a bit more fairly 2016-11-23 10:28:22 -08:00
Wesley W. Terpstra e8e95d4bcf regression: remove cde submodule update 2016-11-23 10:28:22 -08:00
Wesley W. Terpstra a93d34742a rocketchip: bump all submodules (and remove cde) 2016-11-23 10:28:22 -08:00
Wesley W. TerpstraandGitHub 612f96b2af Merge pull request #447 from ucb-bar/axi4-master 
Axi4 master
 2016-11-23 10:23:43 -08:00
Wesley W. Terpstra 1d3cad3671 tilelink2 SourceShrinker: handle degenerate cases for free 2016-11-22 22:17:30 -08:00
Wesley W. Terpstra 1e7d597fd3 rocketchip: don't waste too many sources on the AXI master port 2016-11-22 21:48:41 -08:00
Wesley W. Terpstra c0b27999ea tilelink2 SourceShrinker: a concurrency reducing adapter 2016-11-22 21:43:38 -08:00
Wesley W. Terpstra 0097274ea3 Broadcast: single-cycle response is possible 2016-11-22 20:45:40 -08:00
Wesley W. Terpstra 437be0f36a PositionalMultiQueue: use a UInt instead of Reg(Vec(Bool)) 
This results in much less Verilog to simulate
 2016-11-22 20:39:38 -08:00
Wesley W. Terpstra f9de7173cc PositionalMultiQueue: use 1-write n-read Mem instead of Reg(Vec(...)) 2016-11-22 18:46:11 -08:00
Wesley W. Terpstra d9a203b0f0 PositionalMultiQueue: convert 'next' to a single write port 2016-11-22 18:38:55 -08:00
Wesley W. Terpstra 13190a5de0 rocketchip: re-add AXI4 interface 2016-11-22 17:27:58 -08:00
Wesley W. Terpstra c230580157 coreplex: rename RocketPlex => RocketTiles 2016-11-22 17:27:58 -08:00
Wesley W. Terpstra bbabcf67ff coreplex: width adapter should happen as part of coherence manager 
In the future we will want the L2 to be wider on the backside so that
we can take advantage of fat DDR controllers (256bits/beat).
 2016-11-22 17:27:58 -08:00