riscv/rocket-chip
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Merge pull request #540 from ucb-bar/dedup

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Dedup rocket
This commit is contained in:
Wesley W. Terpstra 2017-01-31 17:16:43 -08:00 committed by GitHub
commit b2ee5e7d38
16 changed files with 227 additions and 227 deletions
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2
chisel3

@ -1 +1 @@
Subproject commit 2a4d4f0ee9fc924ee9ff8a12c7a04a4c8e9a106b
Subproject commit 3ef63639284b2b56f415e1540c58d85d88c360db

2
firrtl

@ -1 +1 @@
Subproject commit 6c00f2c880a536b61196e7ec63fc861d69c8b764
Subproject commit 568f25b221884eeb0db362c902c933f734c7e47e

28
src/main/scala/junctions/hasti.scala
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@ -12,26 +12,26 @@ object HastiConstants
{
// Values for htrans
val SZ_HTRANS = 2
val HTRANS_IDLE = UInt(0, SZ_HTRANS) // No transfer requested, not in a burst
val HTRANS_BUSY = UInt(1, SZ_HTRANS) // No transfer requested, in a burst
val HTRANS_NONSEQ = UInt(2, SZ_HTRANS) // First (potentially only) request in a burst
val HTRANS_SEQ = UInt(3, SZ_HTRANS) // Following requests in a burst
def HTRANS_IDLE = UInt(0, SZ_HTRANS) // No transfer requested, not in a burst
def HTRANS_BUSY = UInt(1, SZ_HTRANS) // No transfer requested, in a burst
def HTRANS_NONSEQ = UInt(2, SZ_HTRANS) // First (potentially only) request in a burst
def HTRANS_SEQ = UInt(3, SZ_HTRANS) // Following requests in a burst
// Values for hburst
val SZ_HBURST = 3
val HBURST_SINGLE = UInt(0, SZ_HBURST) // Single access (no burst)
val HBURST_INCR = UInt(1, SZ_HBURST) // Incrementing burst of arbitrary length, not crossing 1KB
val HBURST_WRAP4 = UInt(2, SZ_HBURST) // 4-beat wrapping burst
val HBURST_INCR4 = UInt(3, SZ_HBURST) // 4-beat incrementing burst
val HBURST_WRAP8 = UInt(4, SZ_HBURST) // 8-beat wrapping burst
val HBURST_INCR8 = UInt(5, SZ_HBURST) // 8-beat incrementing burst
val HBURST_WRAP16 = UInt(6, SZ_HBURST) // 16-beat wrapping burst
val HBURST_INCR16 = UInt(7, SZ_HBURST) // 16-beat incrementing burst
def HBURST_SINGLE = UInt(0, SZ_HBURST) // Single access (no burst)
def HBURST_INCR = UInt(1, SZ_HBURST) // Incrementing burst of arbitrary length, not crossing 1KB
def HBURST_WRAP4 = UInt(2, SZ_HBURST) // 4-beat wrapping burst
def HBURST_INCR4 = UInt(3, SZ_HBURST) // 4-beat incrementing burst
def HBURST_WRAP8 = UInt(4, SZ_HBURST) // 8-beat wrapping burst
def HBURST_INCR8 = UInt(5, SZ_HBURST) // 8-beat incrementing burst
def HBURST_WRAP16 = UInt(6, SZ_HBURST) // 16-beat wrapping burst
def HBURST_INCR16 = UInt(7, SZ_HBURST) // 16-beat incrementing burst
// Values for hresp
val SZ_HRESP = 1
val HRESP_OKAY = UInt(0, SZ_HRESP)
val HRESP_ERROR = UInt(1, SZ_HRESP)
def HRESP_OKAY = UInt(0, SZ_HRESP)
def HRESP_ERROR = UInt(1, SZ_HRESP)
// Values for hsize are identical to TileLink MT_SZ
// ie: 8*2^SZ_HSIZE bit transfers

22
src/main/scala/junctions/nasti.scala
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@ -128,19 +128,19 @@ class NastiReadDataChannel(implicit p: Parameters) extends NastiResponseChannel(
}
object NastiConstants {
val BURST_FIXED = UInt("b00")
val BURST_INCR = UInt("b01")
val BURST_WRAP = UInt("b10")
def BURST_FIXED = UInt("b00")
def BURST_INCR = UInt("b01")
def BURST_WRAP = UInt("b10")
val RESP_OKAY = UInt("b00")
val RESP_EXOKAY = UInt("b01")
val RESP_SLVERR = UInt("b10")
val RESP_DECERR = UInt("b11")
def RESP_OKAY = UInt("b00")
def RESP_EXOKAY = UInt("b01")
def RESP_SLVERR = UInt("b10")
def RESP_DECERR = UInt("b11")
val CACHE_DEVICE_NOBUF = UInt("b0000")
val CACHE_DEVICE_BUF = UInt("b0001")
val CACHE_NORMAL_NOCACHE_NOBUF = UInt("b0010")
val CACHE_NORMAL_NOCACHE_BUF = UInt("b0011")
def CACHE_DEVICE_NOBUF = UInt("b0000")
def CACHE_DEVICE_BUF = UInt("b0001")
def CACHE_NORMAL_NOCACHE_NOBUF = UInt("b0010")
def CACHE_NORMAL_NOCACHE_BUF = UInt("b0011")
def AXPROT(instruction: Bool, nonsecure: Bool, privileged: Bool): UInt =
Cat(instruction, nonsecure, privileged)

36
src/main/scala/rocket/FPU.scala
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@ -19,24 +19,24 @@ case class FPUConfig(
object FPConstants
{
val FCMD_ADD = BitPat("b0??00")
val FCMD_SUB = BitPat("b0??01")
val FCMD_MUL = BitPat("b0??10")
val FCMD_MADD = BitPat("b1??00")
val FCMD_MSUB = BitPat("b1??01")
val FCMD_NMSUB = BitPat("b1??10")
val FCMD_NMADD = BitPat("b1??11")
val FCMD_DIV = BitPat("b?0011")
val FCMD_SQRT = BitPat("b?1011")
val FCMD_SGNJ = BitPat("b??1?0")
val FCMD_MINMAX = BitPat("b?01?1")
val FCMD_CVT_FF = BitPat("b??0??")
val FCMD_CVT_IF = BitPat("b?10??")
val FCMD_CMP = BitPat("b?01??")
val FCMD_MV_XF = BitPat("b?11??")
val FCMD_CVT_FI = BitPat("b??0??")
val FCMD_MV_FX = BitPat("b??1??")
val FCMD_X = BitPat("b?????")
def FCMD_ADD = BitPat("b0??00")
def FCMD_SUB = BitPat("b0??01")
def FCMD_MUL = BitPat("b0??10")
def FCMD_MADD = BitPat("b1??00")
def FCMD_MSUB = BitPat("b1??01")
def FCMD_NMSUB = BitPat("b1??10")
def FCMD_NMADD = BitPat("b1??11")
def FCMD_DIV = BitPat("b?0011")
def FCMD_SQRT = BitPat("b?1011")
def FCMD_SGNJ = BitPat("b??1?0")
def FCMD_MINMAX = BitPat("b?01?1")
def FCMD_CVT_FF = BitPat("b??0??")
def FCMD_CVT_IF = BitPat("b?10??")
def FCMD_CMP = BitPat("b?01??")
def FCMD_MV_XF = BitPat("b?11??")
def FCMD_CVT_FI = BitPat("b??0??")
def FCMD_MV_FX = BitPat("b??1??")
def FCMD_X = BitPat("b?????")
val FCMD_WIDTH = 5
val RM_SZ = 3

10
src/main/scala/rocket/Rocc.scala
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@ -407,11 +407,11 @@ class OpcodeSet(val opcodes: Seq[UInt]) {
}
object OpcodeSet {
val custom0 = new OpcodeSet(Seq(Bits("b0001011")))
val custom1 = new OpcodeSet(Seq(Bits("b0101011")))
val custom2 = new OpcodeSet(Seq(Bits("b1011011")))
val custom3 = new OpcodeSet(Seq(Bits("b1111011")))
val all = custom0 | custom1 | custom2 | custom3
def custom0 = new OpcodeSet(Seq(Bits("b0001011")))
def custom1 = new OpcodeSet(Seq(Bits("b0101011")))
def custom2 = new OpcodeSet(Seq(Bits("b1011011")))
def custom3 = new OpcodeSet(Seq(Bits("b1111011")))
def all = custom0 | custom1 | custom2 | custom3
}
class RoccCommandRouter(opcodes: Seq[OpcodeSet])(implicit p: Parameters)

80
src/main/scala/rocket/consts.scala
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@ -8,54 +8,54 @@ import scala.math._
trait ScalarOpConstants {
val MT_SZ = 3
val MT_X = BitPat("b???")
val MT_B = UInt("b000")
val MT_H = UInt("b001")
val MT_W = UInt("b010")
val MT_D = UInt("b011")
val MT_BU = UInt("b100")
val MT_HU = UInt("b101")
val MT_WU = UInt("b110")
def MT_X = BitPat("b???")
def MT_B = UInt("b000")
def MT_H = UInt("b001")
def MT_W = UInt("b010")
def MT_D = UInt("b011")
def MT_BU = UInt("b100")
def MT_HU = UInt("b101")
def MT_WU = UInt("b110")
def mtSize(mt: UInt) = mt(MT_SZ-2, 0)
def mtSigned(mt: UInt) = !mt(MT_SZ-1)
val SZ_BR = 3
val BR_X = BitPat("b???")
val BR_EQ = UInt(0, 3)
val BR_NE = UInt(1, 3)
val BR_J = UInt(2, 3)
val BR_N = UInt(3, 3)
val BR_LT = UInt(4, 3)
val BR_GE = UInt(5, 3)
val BR_LTU = UInt(6, 3)
val BR_GEU = UInt(7, 3)
def BR_X = BitPat("b???")
def BR_EQ = UInt(0, 3)
def BR_NE = UInt(1, 3)
def BR_J = UInt(2, 3)
def BR_N = UInt(3, 3)
def BR_LT = UInt(4, 3)
def BR_GE = UInt(5, 3)
def BR_LTU = UInt(6, 3)
def BR_GEU = UInt(7, 3)
val A1_X = BitPat("b??")
val A1_ZERO = UInt(0, 2)
val A1_RS1 = UInt(1, 2)
val A1_PC = UInt(2, 2)
def A1_X = BitPat("b??")
def A1_ZERO = UInt(0, 2)
def A1_RS1 = UInt(1, 2)
def A1_PC = UInt(2, 2)
val IMM_X = BitPat("b???")
val IMM_S = UInt(0, 3)
val IMM_SB = UInt(1, 3)
val IMM_U = UInt(2, 3)
val IMM_UJ = UInt(3, 3)
val IMM_I = UInt(4, 3)
val IMM_Z = UInt(5, 3)
def IMM_X = BitPat("b???")
def IMM_S = UInt(0, 3)
def IMM_SB = UInt(1, 3)
def IMM_U = UInt(2, 3)
def IMM_UJ = UInt(3, 3)
def IMM_I = UInt(4, 3)
def IMM_Z = UInt(5, 3)
val A2_X = BitPat("b??")
val A2_ZERO = UInt(0, 2)
val A2_SIZE = UInt(1, 2)
val A2_RS2 = UInt(2, 2)
val A2_IMM = UInt(3, 2)
def A2_X = BitPat("b??")
def A2_ZERO = UInt(0, 2)
def A2_SIZE = UInt(1, 2)
def A2_RS2 = UInt(2, 2)
def A2_IMM = UInt(3, 2)
val X = BitPat("b?")
val N = BitPat("b0")
val Y = BitPat("b1")
def X = BitPat("b?")
def N = BitPat("b0")
def Y = BitPat("b1")
val SZ_DW = 1
val DW_X = X
val DW_32 = Bool(false)
val DW_64 = Bool(true)
val DW_XPR = DW_64
def DW_X = X
def DW_32 = Bool(false)
def DW_64 = Bool(true)
def DW_XPR = DW_64
}

18
src/main/scala/rocket/csr.scala
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@ -103,17 +103,17 @@ object CSR
{
// commands
val SZ = 3
val X = BitPat.dontCare(SZ)
val N = UInt(0,SZ)
val W = UInt(1,SZ)
val S = UInt(2,SZ)
val C = UInt(3,SZ)
val I = UInt(4,SZ)
val R = UInt(5,SZ)
def X = BitPat.dontCare(SZ)
def N = UInt(0,SZ)
def W = UInt(1,SZ)
def S = UInt(2,SZ)
def C = UInt(3,SZ)
def I = UInt(4,SZ)
def R = UInt(5,SZ)
val ADDRSZ = 12
val debugIntCause = new MIP().getWidth
val debugTriggerCause = {
def debugIntCause = new MIP().getWidth
def debugTriggerCause = {
require(debugIntCause >= Causes.all.max)
debugIntCause
}

46
src/main/scala/rocket/dpath_alu.scala
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@ -10,31 +10,31 @@ import Instructions._
object ALU
{
val SZ_ALU_FN = 4
val FN_X = BitPat("b????")
val FN_ADD = UInt(0)
val FN_SL = UInt(1)
val FN_SEQ = UInt(2)
val FN_SNE = UInt(3)
val FN_XOR = UInt(4)
val FN_SR = UInt(5)
val FN_OR = UInt(6)
val FN_AND = UInt(7)
val FN_SUB = UInt(10)
val FN_SRA = UInt(11)
val FN_SLT = UInt(12)
val FN_SGE = UInt(13)
val FN_SLTU = UInt(14)
val FN_SGEU = UInt(15)
def FN_X = BitPat("b????")
def FN_ADD = UInt(0)
def FN_SL = UInt(1)
def FN_SEQ = UInt(2)
def FN_SNE = UInt(3)
def FN_XOR = UInt(4)
def FN_SR = UInt(5)
def FN_OR = UInt(6)
def FN_AND = UInt(7)
def FN_SUB = UInt(10)
def FN_SRA = UInt(11)
def FN_SLT = UInt(12)
def FN_SGE = UInt(13)
def FN_SLTU = UInt(14)
def FN_SGEU = UInt(15)
val FN_DIV = FN_XOR
val FN_DIVU = FN_SR
val FN_REM = FN_OR
val FN_REMU = FN_AND
def FN_DIV = FN_XOR
def FN_DIVU = FN_SR
def FN_REM = FN_OR
def FN_REMU = FN_AND
val FN_MUL = FN_ADD
val FN_MULH = FN_SL
val FN_MULHSU = FN_SLT
val FN_MULHU = FN_SLTU
def FN_MUL = FN_ADD
def FN_MULH = FN_SL
def FN_MULHSU = FN_SLT
def FN_MULHU = FN_SLTU
def isMulFN(fn: UInt, cmp: UInt) = fn(1,0) === cmp(1,0)
def isSub(cmd: UInt) = cmd(3)

40
src/main/scala/uncore/Consts.scala
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@ -9,26 +9,26 @@ object MemoryOpConstants extends MemoryOpConstants
trait MemoryOpConstants {
val NUM_XA_OPS = 9
val M_SZ = 5
val M_X = BitPat("b?????");
val M_XRD = UInt("b00000"); // int load
val M_XWR = UInt("b00001"); // int store
val M_PFR = UInt("b00010"); // prefetch with intent to read
val M_PFW = UInt("b00011"); // prefetch with intent to write
val M_XA_SWAP = UInt("b00100");
val M_FLUSH_ALL = UInt("b00101") // flush all lines
val M_XLR = UInt("b00110");
val M_XSC = UInt("b00111");
val M_XA_ADD = UInt("b01000");
val M_XA_XOR = UInt("b01001");
val M_XA_OR = UInt("b01010");
val M_XA_AND = UInt("b01011");
val M_XA_MIN = UInt("b01100");
val M_XA_MAX = UInt("b01101");
val M_XA_MINU = UInt("b01110");
val M_XA_MAXU = UInt("b01111");
val M_FLUSH = UInt("b10000") // write back dirty data and cede R/W permissions
val M_PRODUCE = UInt("b10001") // write back dirty data and cede W permissions
val M_CLEAN = UInt("b10011") // write back dirty data and retain R/W permissions
def M_X = BitPat("b?????");
def M_XRD = UInt("b00000"); // int load
def M_XWR = UInt("b00001"); // int store
def M_PFR = UInt("b00010"); // prefetch with intent to read
def M_PFW = UInt("b00011"); // prefetch with intent to write
def M_XA_SWAP = UInt("b00100");
def M_FLUSH_ALL = UInt("b00101") // flush all lines
def M_XLR = UInt("b00110");
def M_XSC = UInt("b00111");
def M_XA_ADD = UInt("b01000");
def M_XA_XOR = UInt("b01001");
def M_XA_OR = UInt("b01010");
def M_XA_AND = UInt("b01011");
def M_XA_MIN = UInt("b01100");
def M_XA_MAX = UInt("b01101");
def M_XA_MINU = UInt("b01110");
def M_XA_MAXU = UInt("b01111");
def M_FLUSH = UInt("b10000") // write back dirty data and cede R/W permissions
def M_PRODUCE = UInt("b10001") // write back dirty data and cede W permissions
def M_CLEAN = UInt("b10011") // write back dirty data and retain R/W permissions
def isAMO(cmd: UInt) = cmd(3) || cmd === M_XA_SWAP
def isPrefetch(cmd: UInt) = cmd === M_PFR || cmd === M_PFW

36
src/main/scala/uncore/ahb/Protocol.scala
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@ -12,28 +12,28 @@ object AHBParameters
val protBits = 4
val sizeBits = 3 // 8*2^s
val TRANS_IDLE = UInt(0, width = transBits) // No transfer requested, not in a burst
val TRANS_BUSY = UInt(1, width = transBits) // No transfer requested, in a burst
val TRANS_NONSEQ = UInt(2, width = transBits) // First (potentially only) request in a burst
val TRANS_SEQ = UInt(3, width = transBits) // Following requests in a burst
def TRANS_IDLE = UInt(0, width = transBits) // No transfer requested, not in a burst
def TRANS_BUSY = UInt(1, width = transBits) // No transfer requested, in a burst
def TRANS_NONSEQ = UInt(2, width = transBits) // First (potentially only) request in a burst
def TRANS_SEQ = UInt(3, width = transBits) // Following requests in a burst
val BURST_SINGLE = UInt(0, width = burstBits) // Single access (no burst)
val BURST_INCR = UInt(1, width = burstBits) // Incrementing burst of arbitrary length, not crossing 1KB
val BURST_WRAP4 = UInt(2, width = burstBits) // 4-beat wrapping burst
val BURST_INCR4 = UInt(3, width = burstBits) // 4-beat incrementing burst
val BURST_WRAP8 = UInt(4, width = burstBits) // 8-beat wrapping burst
val BURST_INCR8 = UInt(5, width = burstBits) // 8-beat incrementing burst
val BURST_WRAP16 = UInt(6, width = burstBits) // 16-beat wrapping burst
val BURST_INCR16 = UInt(7, width = burstBits) // 16-beat incrementing burst
def BURST_SINGLE = UInt(0, width = burstBits) // Single access (no burst)
def BURST_INCR = UInt(1, width = burstBits) // Incrementing burst of arbitrary length, not crossing 1KB
def BURST_WRAP4 = UInt(2, width = burstBits) // 4-beat wrapping burst
def BURST_INCR4 = UInt(3, width = burstBits) // 4-beat incrementing burst
def BURST_WRAP8 = UInt(4, width = burstBits) // 8-beat wrapping burst
def BURST_INCR8 = UInt(5, width = burstBits) // 8-beat incrementing burst
def BURST_WRAP16 = UInt(6, width = burstBits) // 16-beat wrapping burst
def BURST_INCR16 = UInt(7, width = burstBits) // 16-beat incrementing burst
val maxTransfer = 16
val RESP_OKAY = Bool(false)
val RESP_ERROR = Bool(true)
def RESP_OKAY = Bool(false)
def RESP_ERROR = Bool(true)
val PROT_DATA = UInt(1, width = protBits)
val PROT_PRIVILEDGED = UInt(2, width = protBits)
val PROT_BUFFERABLE = UInt(4, width = protBits)
val PROT_CACHEABLE = UInt(8, width = protBits)
def PROT_DATA = UInt(1, width = protBits)
def PROT_PRIVILEDGED = UInt(2, width = protBits)
def PROT_BUFFERABLE = UInt(4, width = protBits)
def PROT_CACHEABLE = UInt(8, width = protBits)
def PROT_DEFAULT = PROT_DATA | PROT_PRIVILEDGED
}

6
src/main/scala/uncore/apb/Protocol.scala
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@ -9,8 +9,8 @@ object APBParameters
// These are all fixed by the AHB standard:
val protBits = 3
val PROT_PRIVILEDGED = UInt(1, width = protBits)
val PROT_NONSECURE = UInt(2, width = protBits)
val PROT_INSTRUCTION = UInt(4, width = protBits)
def PROT_PRIVILEDGED = UInt(1, width = protBits)
def PROT_NONSECURE = UInt(2, width = protBits)
def PROT_INSTRUCTION = UInt(4, width = protBits)
def PROT_DEFAULT = PROT_PRIVILEDGED
}

28
src/main/scala/uncore/axi4/Protocol.scala
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@ -17,21 +17,21 @@ object AXI4Parameters
val qosBits = 4
val respBits = 2
val CACHE_RALLOCATE = UInt(8, width = cacheBits)
val CACHE_WALLOCATE = UInt(4, width = cacheBits)
val CACHE_MODIFIABLE = UInt(2, width = cacheBits)
val CACHE_BUFFERABLE = UInt(1, width = cacheBits)
def CACHE_RALLOCATE = UInt(8, width = cacheBits)
def CACHE_WALLOCATE = UInt(4, width = cacheBits)
def CACHE_MODIFIABLE = UInt(2, width = cacheBits)
def CACHE_BUFFERABLE = UInt(1, width = cacheBits)
val PROT_PRIVILEDGED = UInt(1, width = protBits)
val PROT_INSECURE = UInt(2, width = protBits)
val PROT_INSTRUCTION = UInt(4, width = protBits)
def PROT_PRIVILEDGED = UInt(1, width = protBits)
def PROT_INSECURE = UInt(2, width = protBits)
def PROT_INSTRUCTION = UInt(4, width = protBits)
val BURST_FIXED = UInt(0, width = burstBits)
val BURST_INCR = UInt(1, width = burstBits)
val BURST_WRAP = UInt(2, width = burstBits)
def BURST_FIXED = UInt(0, width = burstBits)
def BURST_INCR = UInt(1, width = burstBits)
def BURST_WRAP = UInt(2, width = burstBits)
val RESP_OKAY = UInt(0, width = respBits)
val RESP_EXOKAY = UInt(1, width = respBits)
val RESP_SLVERR = UInt(2, width = respBits)
val RESP_DECERR = UInt(3, width = respBits)
def RESP_OKAY = UInt(0, width = respBits)
def RESP_EXOKAY = UInt(1, width = respBits)
def RESP_SLVERR = UInt(2, width = respBits)
def RESP_DECERR = UInt(3, width = respBits)
}

8
src/main/scala/uncore/tilelink2/Broadcast.scala
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@ -291,10 +291,10 @@ class TLBroadcastTracker(id: Int, lineBytes: Int, probeCountBits: Int, bufferles
object TLBroadcastConstants
{
val TRANSFORM_T = UInt(3)
val TRANSFORM_B = UInt(2)
val DROP = UInt(1)
val PASS = UInt(0)
def TRANSFORM_T = UInt(3)
def TRANSFORM_B = UInt(2)
def DROP = UInt(1)
def PASS = UInt(0)
}
class TLBroadcastData(params: TLBundleParameters) extends TLBundleBase(params)

84
src/main/scala/uncore/tilelink2/Bundles.scala
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@ -16,25 +16,25 @@ abstract class TLBundleBase(params: TLBundleParameters) extends GenericParameter
object TLMessages
{
// A B C D E
val PutFullData = UInt(0) // . . => AccessAck
val PutPartialData = UInt(1) // . . => AccessAck
val ArithmeticData = UInt(2) // . . => AccessAckData
val LogicalData = UInt(3) // . . => AccessAckData
val Get = UInt(4) // . . => AccessAckData
val Hint = UInt(5) // . . => HintAck
val Acquire = UInt(6) // . => Grant[Data]
val Probe = UInt(6) // . => ProbeAck[Data]
val AccessAck = UInt(0) // . .
val AccessAckData = UInt(1) // . .
val HintAck = UInt(2) // . .
val ProbeAck = UInt(4) // .
val ProbeAckData = UInt(5) // .
val Release = UInt(6) // . => ReleaseAck
val ReleaseData = UInt(7) // . => ReleaseAck
val Grant = UInt(4) // . => GrantAck
val GrantData = UInt(5) // . => GrantAck
val ReleaseAck = UInt(6) // .
val GrantAck = UInt(0) // .
def PutFullData = UInt(0) // . . => AccessAck
def PutPartialData = UInt(1) // . . => AccessAck
def ArithmeticData = UInt(2) // . . => AccessAckData
def LogicalData = UInt(3) // . . => AccessAckData
def Get = UInt(4) // . . => AccessAckData
def Hint = UInt(5) // . . => HintAck
def Acquire = UInt(6) // . => Grant[Data]
def Probe = UInt(6) // . => ProbeAck[Data]
def AccessAck = UInt(0) // . .
def AccessAckData = UInt(1) // . .
def HintAck = UInt(2) // . .
def ProbeAck = UInt(4) // .
def ProbeAckData = UInt(5) // .
def Release = UInt(6) // . => ReleaseAck
def ReleaseData = UInt(7) // . => ReleaseAck
def Grant = UInt(4) // . => GrantAck
def GrantData = UInt(5) // . => GrantAck
def ReleaseAck = UInt(6) // .
def GrantAck = UInt(0) // .
def isA(x: UInt) = x <= Acquire
def isB(x: UInt) = x <= Probe
@ -58,27 +58,27 @@ object TLPermissions
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
val toT = UInt(0, bdWidth)
val toB = UInt(1, bdWidth)
val toN = UInt(2, bdWidth)
def toT = UInt(0, bdWidth)
def toB = UInt(1, bdWidth)
def toN = UInt(2, bdWidth)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
val NtoB = UInt(0, aWidth)
val NtoT = UInt(1, aWidth)
val BtoT = UInt(2, aWidth)
def NtoB = UInt(0, aWidth)
def NtoT = UInt(1, aWidth)
def BtoT = UInt(2, aWidth)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
val TtoB = UInt(0, cWidth)
val TtoN = UInt(1, cWidth)
val BtoN = UInt(2, cWidth)
def TtoB = UInt(0, cWidth)
def TtoN = UInt(1, cWidth)
def BtoN = UInt(2, cWidth)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck)
val TtoT = UInt(3, cWidth)
val BtoB = UInt(4, cWidth)
val NtoN = UInt(5, cWidth)
def TtoT = UInt(3, cWidth)
def BtoB = UInt(4, cWidth)
def NtoN = UInt(5, cWidth)
def isReport(x: UInt) = x <= NtoN
}
@ -87,18 +87,18 @@ object TLAtomics
val width = 3
// Arithmetic types
val MIN = UInt(0, width)
val MAX = UInt(1, width)
val MINU = UInt(2, width)
val MAXU = UInt(3, width)
val ADD = UInt(4, width)
def MIN = UInt(0, width)
def MAX = UInt(1, width)
def MINU = UInt(2, width)
def MAXU = UInt(3, width)
def ADD = UInt(4, width)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
val XOR = UInt(0, width)
val OR = UInt(1, width)
val AND = UInt(2, width)
val SWAP = UInt(3, width)
def XOR = UInt(0, width)
def OR = UInt(1, width)
def AND = UInt(2, width)
def SWAP = UInt(3, width)
def isLogical(x: UInt) = x <= SWAP
}
@ -106,8 +106,8 @@ object TLHints
{
val width = 1
val PREFETCH_READ = UInt(0, width)
val PREFETCH_WRITE = UInt(1, width)
def PREFETCH_READ = UInt(0, width)
def PREFETCH_WRITE = UInt(1, width)
}
sealed trait TLChannel extends TLBundleBase {

8
src/main/scala/uncore/tilelink2/Metadata.scala
View File

@ -11,10 +11,10 @@ import uncore.constants.MemoryOpConstants
object ClientStates {
val width = 2
val Nothing = UInt(0, width)
val Branch = UInt(1, width)
val Trunk = UInt(2, width)
val Dirty = UInt(3, width)
def Nothing = UInt(0, width)
def Branch = UInt(1, width)
def Trunk = UInt(2, width)
def Dirty = UInt(3, width)
def hasReadPermission(state: UInt): Bool = state > Nothing
def hasWritePermission(state: UInt): Bool = state > Branch