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Merge pull request #537 from ucb-bar/l2-banks-together

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BankedL2Config: use the same LazyModule for all L2 banks
This commit is contained in:
Wesley W. Terpstra
2017-01-30 15:39:04 -08:00
committed by GitHub
parent b567a2a356 dc66c8857f
commit 9c0cc6fdf4
4 changed files with 19 additions and 11 deletions
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7
src/main/scala/coreplex/BaseCoreplex.scala
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@@ -22,15 +22,16 @@ case class BroadcastConfig(
case object BroadcastConfig extends Field[BroadcastConfig]
/** L2 memory subsystem configuration */
case class BankedL2Geometry(bank: Int, banks: Int, channel: Int, channels: Int)
case class BankedL2Config(
nMemoryChannels: Int = 1,
nBanksPerChannel: Int = 1,
coherenceManager: (Parameters, CoreplexNetwork, BankedL2Geometry) => (TLInwardNode, TLOutwardNode) = { case (q, _, _) =>
coherenceManager: (Parameters, CoreplexNetwork) => (TLInwardNode, TLOutwardNode) = { case (q, _) =>
implicit val p = q
val BroadcastConfig(nTrackers, bufferless) = p(BroadcastConfig)
val bh = LazyModule(new TLBroadcast(p(CacheBlockBytes), nTrackers, bufferless))
(bh.node, TLWidthWidget(p(L1toL2Config).beatBytes)(bh.node))
val ww = LazyModule(new TLWidthWidget(p(L1toL2Config).beatBytes))
ww.node :*= bh.node
(bh.node, ww.node)
}) {
val nBanks = nMemoryChannels*nBanksPerChannel
}

6
src/main/scala/coreplex/Configs.scala
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@@ -144,10 +144,12 @@ class WithBufferlessBroadcastHub extends Config((site, here, up) => {
* DO NOT use this configuration.
*/
class WithStatelessBridge extends Config((site, here, up) => {
case BankedL2Config => up(BankedL2Config, site).copy(coherenceManager = { case (q, _, _) =>
case BankedL2Config => up(BankedL2Config, site).copy(coherenceManager = { case (q, _) =>
implicit val p = q
val cork = LazyModule(new TLCacheCork(unsafe = true))
(cork.node, TLWidthWidget(p(L1toL2Config).beatBytes)(cork.node))
val ww = LazyModule(new TLWidthWidget(p(L1toL2Config).beatBytes))
ww.node :*= cork.node
(cork.node, ww.node)
})
case DCacheKey => up(DCacheKey, site).copy(nMSHRs = 0)
})

6
src/main/scala/coreplex/CoreplexNetwork.scala
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@@ -77,13 +77,13 @@ trait BankedL2CoherenceManagers extends CoreplexNetwork {
val mem = TLOutputNode()
for (channel <- 0 until l2Config.nMemoryChannels) {
val bankBar = LazyModule(new TLXbar)
val (in, out) = l2Config.coherenceManager(p, this)
in :*= l1tol2.node
mem := bankBar.node
val mask = ~BigInt((l2Config.nBanksPerChannel-1) * l1tol2_lineBytes)
for (bank <- 0 until l2Config.nBanksPerChannel) {
val geometry = BankedL2Geometry(bank, l2Config.nBanksPerChannel, channel, l2Config.nMemoryChannels)
val (in, out) = l2Config.coherenceManager(p, this, geometry)
in := l1tol2.node
bankBar.node := TLFilter(AddressSet(bank * l1tol2_lineBytes, mask))(out)
}
}

11
src/main/scala/diplomacy/LazyModule.scala
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@@ -27,10 +27,15 @@ abstract class LazyModule()(implicit val p: Parameters)
m.getName != "children"
}.flatMap { m =>
if (classOf[LazyModule].isAssignableFrom(m.getReturnType)) {
Seq((m.getName, m.invoke(this)))
val obj = m.invoke(this)
if (obj eq null) Seq() else Seq((m.getName, obj))
} else if (classOf[Seq[LazyModule]].isAssignableFrom(m.getReturnType)) {
m.invoke(this).asInstanceOf[Seq[Object]].zipWithIndex.map { case (l, i) =>
(m.getName + "_" + i, l)
val obj = m.invoke(this)
if (obj eq null) Seq() else {
val seq = try { obj.asInstanceOf[Seq[Object]] } catch { case _ => null }
if (seq eq null) Seq() else {
seq.zipWithIndex.map { case (l, i) => (m.getName + "_" + i, l) }
}
}
} else Seq()
}