Merge pull request #537 from ucb-bar/l2-banks-together
BankedL2Config: use the same LazyModule for all L2 banks
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commit
9c0cc6fdf4
@ -22,15 +22,16 @@ case class BroadcastConfig(
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case object BroadcastConfig extends Field[BroadcastConfig]
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/** L2 memory subsystem configuration */
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case class BankedL2Geometry(bank: Int, banks: Int, channel: Int, channels: Int)
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case class BankedL2Config(
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nMemoryChannels: Int = 1,
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nBanksPerChannel: Int = 1,
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coherenceManager: (Parameters, CoreplexNetwork, BankedL2Geometry) => (TLInwardNode, TLOutwardNode) = { case (q, _, _) =>
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coherenceManager: (Parameters, CoreplexNetwork) => (TLInwardNode, TLOutwardNode) = { case (q, _) =>
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implicit val p = q
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val BroadcastConfig(nTrackers, bufferless) = p(BroadcastConfig)
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val bh = LazyModule(new TLBroadcast(p(CacheBlockBytes), nTrackers, bufferless))
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(bh.node, TLWidthWidget(p(L1toL2Config).beatBytes)(bh.node))
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val ww = LazyModule(new TLWidthWidget(p(L1toL2Config).beatBytes))
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ww.node :*= bh.node
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(bh.node, ww.node)
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}) {
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val nBanks = nMemoryChannels*nBanksPerChannel
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}
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@ -144,10 +144,12 @@ class WithBufferlessBroadcastHub extends Config((site, here, up) => {
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* DO NOT use this configuration.
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*/
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class WithStatelessBridge extends Config((site, here, up) => {
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case BankedL2Config => up(BankedL2Config, site).copy(coherenceManager = { case (q, _, _) =>
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case BankedL2Config => up(BankedL2Config, site).copy(coherenceManager = { case (q, _) =>
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implicit val p = q
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val cork = LazyModule(new TLCacheCork(unsafe = true))
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(cork.node, TLWidthWidget(p(L1toL2Config).beatBytes)(cork.node))
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val ww = LazyModule(new TLWidthWidget(p(L1toL2Config).beatBytes))
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ww.node :*= cork.node
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(cork.node, ww.node)
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})
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case DCacheKey => up(DCacheKey, site).copy(nMSHRs = 0)
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})
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@ -77,13 +77,13 @@ trait BankedL2CoherenceManagers extends CoreplexNetwork {
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val mem = TLOutputNode()
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for (channel <- 0 until l2Config.nMemoryChannels) {
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val bankBar = LazyModule(new TLXbar)
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val (in, out) = l2Config.coherenceManager(p, this)
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in :*= l1tol2.node
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mem := bankBar.node
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val mask = ~BigInt((l2Config.nBanksPerChannel-1) * l1tol2_lineBytes)
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for (bank <- 0 until l2Config.nBanksPerChannel) {
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val geometry = BankedL2Geometry(bank, l2Config.nBanksPerChannel, channel, l2Config.nMemoryChannels)
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val (in, out) = l2Config.coherenceManager(p, this, geometry)
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in := l1tol2.node
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bankBar.node := TLFilter(AddressSet(bank * l1tol2_lineBytes, mask))(out)
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}
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}
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@ -27,10 +27,15 @@ abstract class LazyModule()(implicit val p: Parameters)
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m.getName != "children"
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}.flatMap { m =>
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if (classOf[LazyModule].isAssignableFrom(m.getReturnType)) {
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Seq((m.getName, m.invoke(this)))
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val obj = m.invoke(this)
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if (obj eq null) Seq() else Seq((m.getName, obj))
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} else if (classOf[Seq[LazyModule]].isAssignableFrom(m.getReturnType)) {
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m.invoke(this).asInstanceOf[Seq[Object]].zipWithIndex.map { case (l, i) =>
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(m.getName + "_" + i, l)
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val obj = m.invoke(this)
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if (obj eq null) Seq() else {
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val seq = try { obj.asInstanceOf[Seq[Object]] } catch { case _ => null }
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if (seq eq null) Seq() else {
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seq.zipWithIndex.map { case (l, i) => (m.getName + "_" + i, l) }
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}
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}
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} else Seq()
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}
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