Merge pull request #523 from ucb-bar/buffer-move
coreplex: move TLBuffers for L2 and socBus
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commit
b3ef146805
@ -34,9 +34,8 @@ trait CoreplexNetwork extends HasCoreplexParameters {
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l1tol2.node)))
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mmio :=
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TLBuffer()(
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TLWidthWidget(l1tol2_beatBytes)(
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l1tol2.node))
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l1tol2.node)
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}
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trait CoreplexNetworkBundle extends HasCoreplexParameters {
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@ -78,8 +77,8 @@ trait BankedL2CoherenceManagers extends CoreplexNetwork {
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val mask = ~BigInt((l2Config.nBanksPerChannel-1) * l1tol2_lineBytes)
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for (i <- 0 until l2Config.nBanksPerChannel) {
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val (in, out) = l2Config.coherenceManager(p)
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in := TLFilter(AddressSet(i * l1tol2_lineBytes, mask))(l1tol2.node)
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bankBar.node := out
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in := l1tol2.node
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bankBar.node := TLFilter(AddressSet(i * l1tol2_lineBytes, mask))(out)
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}
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}
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}
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@ -99,7 +98,7 @@ trait BankedL2CoherenceManagersModule extends CoreplexNetworkModule {
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trait HasL2MasterPort extends CoreplexNetwork {
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val module: HasL2MasterPortModule
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val l2in = TLInputNode()
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l1tol2.node := l2in
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l1tol2.node := TLBuffer()(l2in)
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}
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trait HasL2MasterPortBundle extends CoreplexNetworkBundle {
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