riscv/rocket-chip
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a857b08c59
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280 Commits

Author SHA1 Message Date
Andrew Waterman
a857b08c59 [rocket] compute D$ tag bits based upon # of arbiter ports 2016-08-09 14:40:48 -07:00
Andrew Waterman
5d4f6383f2 [rocket] Automatically kill D$ access on address exceptions 
Doing this internally to the cache eliminates a long control path
from the cache to the core and back to the cache.
 2016-08-02 17:20:49 -07:00
Andrew Waterman
832e56d3c7 Fix toBits/toUInt/toSInt deprecation warnings 2016-07-31 17:13:52 -07:00
Howard Mao
dcfcac9530 fix LRSC issue (RocketChip issue #86) 
It was possible that the result of a store-conditional could get lost if it
did not depend on the result of the corresponding load-reserved.

This was because the MSHR does not update the client state based on the
secondary requests. So the LR would acquire the line in clientExcusiveClean,
but then we would fail to update the metadata array to change the state
to clientExclusiveDirty.

The solution is to track whether a secondary acquire would cause the
line to be dirty. If so, use M_XWR instead of the primary command to
generate the update coherence state.
 2016-07-26 18:41:52 -07:00
Howard Mao
2723b2f515 fix issues in SimpleHellaCacheIF and document the changes 2016-07-18 17:02:47 -07:00
Andrew Waterman
d78f1aacd0 Clean up some zero-width wire cases using UInt.extract 2016-07-14 22:08:01 -07:00
Howard Mao
f7b392306e make sure SimpleHellaCacheIF can work with blocking DCache 2016-07-07 18:59:23 -07:00
Andrew Waterman
25fdabdd59 Don't implicitly create Vecs, since they're heavyweight 2016-07-06 01:41:31 -07:00
Howard Mao
a9e0a5e2df changes to imports after uncore refactor 2016-06-28 14:09:31 -07:00
Andrew Waterman
60bddddfe6 Merge sptbr and sasid 2016-06-17 18:29:05 -07:00
Colin Schmidt
2c325151bf pass invalidate_lr through simple cache interface (#45) 2016-06-09 17:22:36 -07:00
Andrew Waterman
51379621d6 Flush blocking D$ on FENCE.I 2016-05-31 19:27:28 -07:00
Andrew Waterman
0c50bfcfb3 Work around more zero-width wire cases 2016-05-25 21:47:48 -07:00
Wesley W. Terpstra
e19c5e5d2c IOMSHR: support atomic operations 2016-05-24 15:00:50 -07:00
Howard Mao
f228309bd1 add assertion to make sure SimpleHellaCacheIF doesn't get exception 2016-05-20 16:30:27 -07:00
Andrew Waterman
4aef567a80 Fix MMIO bug: replay_next wasn't set 2016-05-13 17:59:53 -07:00
Albert Ou
0ff4fd0ccd Fix IOMSHR to send finishes for stores 2016-04-30 22:20:29 -07:00
Andrew Waterman
fe8c91f620 Fix IOMSHR state machine bug 
Sending the finish too early causes the CPU response to get dropped.

attn @zhemao
 2016-04-26 15:32:25 -07:00
Andrew Waterman
d93677a343 Support larger cache sets when not using VM 2016-04-26 15:31:32 -07:00
Howard Mao
b7527268bb use address map instead of MMIOBase to find size of memory 2016-04-21 18:44:39 -07:00
Andrew Waterman
51e0870e23 Separate I$ and D$ interface signals that span clock cycles 
For example, Decopuled[HellaCacheReq].bits.kill doesn't make sense,
since it doesn't come the same cycle as ready/valid.
 2016-04-01 19:30:39 -07:00
Andrew Waterman
72f7f71eb5 No need to allow finishes to be sent in s_refill_resp state 
This is a hold-over from when writebacks needed finish messages.
 2016-04-01 16:19:57 -07:00
Henry Cook
78bc18736e LRSC startvation fix: HellaCache generates its own Finish messages again. 2016-04-01 16:04:25 -07:00
Henry Cook
54dd82ff76 bugfix for WB data buffer 2016-03-31 17:53:49 -07:00
Christopher Celio
1792d01ce1 fix leaky assert in nbdcache 
Squash of #33.
 2016-03-31 15:56:14 -07:00
Andrew Waterman
1ae6d09751 Slightly ameliorate D$->I$ critical path via scoreboard 2016-03-25 15:29:32 -07:00
Andrew Waterman
8d1ba4d1ec Remove hard-coded XLEN values from D$ 2016-03-24 14:52:12 -07:00
Andrew Waterman
7ae44d4905 Add RV32 support 2016-03-10 17:32:00 -08:00
Howard Mao
7937fbf074 fix number of IOMSHRs at 1 2016-01-29 14:51:56 -08:00
Howard Mao
77e068c153 fix Chisel3 compat issue in SimpleHellaCacheIF 2016-01-14 22:42:44 -08:00
Howard Mao
120361226d fix more Chisel3 deprecations 2016-01-14 14:46:31 -08:00
Andrew Waterman
6d1bf5c014 Use generic LoadGen/StoreGen 2015-11-24 18:13:33 -08:00
Howard Mao
b0a06a77db fix a few Chisel3 compat issues 2015-11-20 13:33:15 -08:00
Howard Mao
19daee10f0 use default constructors for IOMSHR acquire construction 2015-11-12 15:54:05 -08:00
jackkoenig
1e259a55da Fix SimpleHellaCacheIF assumption about receiving rejected request back 2 cycles later 2015-11-08 21:16:31 -08:00
Henry Cook
4f8468b60f depend on external cde library 2015-10-21 18:19:23 -07:00
Howard Mao
0b7c828b5d go back to using standard LockingArbiter 2015-10-21 09:15:51 -07:00
Howard Mao
c68d9f8137 make ProbeUnit state machine easier to understand 2015-10-20 23:25:23 -07:00
Henry Cook
1a1185be3f Vectorize ROCC and Tile memory interfaces 2015-10-20 15:02:24 -07:00
Henry Cook
6f8997bee9 Minor refactor of StoreGen/AMOALU. 2015-10-16 19:12:46 -07:00
Henry Cook
68cb54bc68 refactor tilelink params 2015-10-14 12:14:36 -07:00
Henry Cook
84576650b5 Removed all traces of params 2015-10-05 21:48:05 -07:00
Howard Mao
19656e4abe make sure to generate release from clean coh state on probe miss 2015-09-30 16:58:18 -07:00
Andrew Waterman
833909a2b5 Chisel3 compatibility fixes 2015-09-30 14:36:26 -07:00
Howard Mao
2f3d15675c fix DataArray writemask in L1D 2015-09-28 16:02:39 -07:00
Andrew Waterman
b93a94597c Remove needless control logic 2015-09-27 13:31:52 -07:00
Andrew Waterman
c3fff12ff0 Revert "replace remaining uses of Vec.fill" 
This reverts commit f7a0d125e83f8ca59d9913bb1db79cef5a6d344a.
 2015-09-25 17:09:06 -07:00
Andrew Waterman
0bfb2962a6 Assume coh.isRead returns true for store-conditional 
This requires an uncore update.
 2015-09-25 15:26:11 -07:00
Howard Mao
a66bdb1956 replace remaining uses of Vec.fill 2015-09-24 17:53:26 -07:00
Howard Mao
9eb988a4c6 make sure access to invalid physical address treated as exception 2015-09-22 10:11:43 -07:00