riscv/rocket-chip
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Author SHA1 Message Date
Howard Mao
2e63fb291a put sensible defaults for NASTI channel constructors 2015-09-25 10:09:25 -07:00
Howard Mao
0d763524ef make sure conf address map scales with number of cores 2015-09-25 09:41:19 -07:00
Howard Mao
5e3f9115d3 make sure HTIF mem_mb doesn't exceed MMIOBase 2015-09-25 09:02:35 -07:00
Schuyler Eldridge
f200d0947a Force C++ emulator to always use 1GB for MEM_SIZE 
Fixes #17
 2015-09-24 23:56:41 -04:00
Howard Mao
c20ed350a0 even more Chisel3 compatability changes 2015-09-24 17:55:41 -07:00
Howard Mao
a66bdb1956 replace remaining uses of Vec.fill 2015-09-24 17:53:26 -07:00
Howard Mao
88b15dba60 replace remaining uses of Vec.fill 2015-09-24 17:51:38 -07:00
Howard Mao
d1f2d40a90 replace remaining uses of Vec.fill 2015-09-24 17:50:09 -07:00
Howard Mao
3ff830e118 ReorderQueue uses Vec of Bools instead of Bits for roq_free 2015-09-24 17:43:53 -07:00
Howard Mao
1c0111cc70 uncore merge commit 2015-09-24 17:10:45 -07:00
Howard Mao
83740dfaa5 Merge branch 'master' of github.com:ucb-bar/uncore 2015-09-24 17:10:09 -07:00
Howard Mao
8d4d8680bf replace NASTIMasterIO and NASTISlaveIO with NASTIIO 2015-09-24 16:59:13 -07:00
Howard Mao
4a85c5a510 pull in hardfloat fixes 2015-09-24 16:58:49 -07:00
Howard Mao
3b86790c3f replace NASTIMasterIO and NASTISlaveIO with NASTIIO 2015-09-24 16:58:20 -07:00
Howard Mao
e3d2207c72 Chisel3 compat: merge NASTIMasterIO and NASTISlaveIO so we do not depend on flip() modifying the object 2015-09-24 16:57:50 -07:00
ducky
ee6754daca Fix clone -> cloneType 2015-09-24 16:18:25 -07:00
Scott Beamer
fbc6e695d3 remove bugs from float_fix 2015-09-23 16:11:47 -07:00
Scott Beamer
56daea793a allow float_fix to take stdin (for piping) 2015-09-23 16:09:09 -07:00
Howard Mao
38a9b23ce7 add a flag to only log and dump after a certain number of cycles 2015-09-22 10:32:31 -07:00
Howard Mao
4496e8d4e2 make sure htif_emulator properly sets memory size 2015-09-22 10:32:31 -07:00
Howard Mao
56ecdff52d Implement NASTI-based Mem/IO interconnect 2015-09-22 10:32:31 -07:00
Howard Mao
ee65f6a84d get rid of Vec.fill in IOs 2015-09-22 10:30:09 -07:00
Howard Mao
9eb988a4c6 make sure access to invalid physical address treated as exception 2015-09-22 10:11:43 -07:00
Howard Mao
16c748576a don't mux data_word_bypass between IOMSHR and cache 2015-09-22 10:10:57 -07:00
Howard Mao
d89bcd3922 modify csr file to bring in line with HTIF changes 2015-09-22 10:10:57 -07:00
Howard Mao
382faba4a6 Implement bypassing L1 data cache for MMIO 2015-09-22 10:10:57 -07:00
Howard Mao
b4d21148ec get rid of NASTI error assertion 2015-09-22 09:43:42 -07:00
Howard Mao
64ab45e2e4 add RWX permission bits to address map 2015-09-22 09:43:22 -07:00
Howard Mao
27745204eb ErrorSlave returns response of correct length for reads 2015-09-22 09:42:57 -07:00
Andrew Waterman
e72e5a34b5 Fix storage of SP values in DP registers 
The SFMA was zero-extending the SP value to 65 bits, rather than filling
the upper 32 bits with 1s.  This meant that an FSD + FLD of that register
would not restore the value properly.

Also, minor code cleanup.
 2015-09-21 12:20:44 -07:00
Andrew Waterman
c6bcc832a1 Chisel3: Don't use Vec.fill for IOs 2015-09-20 13:43:56 -07:00
Andrew Waterman
fd58c52250 Update to latest chisel 2015-09-20 13:37:53 -07:00
Howard Mao
4db6124b2a NASTIErrorSlave should print address 2015-09-18 09:42:41 -07:00
Howard Mao
8b2341b1b1 use reorder queue instead of extra tag bit to determine TL g_type in NASTI -> TL converter 2015-09-18 09:41:37 -07:00
Colin Schmidt
6f85ed191e Add rocketchip_addons to the list of chisel srcs requiring rebuild 2015-09-16 12:28:03 -07:00
Colin Schmidt
7ecb936bf5 Remove -j from "make run-bmark-tests" in travis 
+currently causes inconsistency in build success
+unclear what root cause is
 2015-09-16 12:27:05 -07:00
Scott Beamer
de81762f7c faster and more conservative float_fix 2015-09-15 17:19:29 -07:00
Scott Beamer
7e25b1ce03 cleaner/faster comlog without linear search 2015-09-15 17:19:29 -07:00
Christopher Celio
76bf1da310 [commitlog] zero-extend SP write-back values 2015-09-15 16:47:26 -07:00
Scott Beamer
3b48d8569c [commitlog] don't print out writebacks to x0 2015-09-15 16:47:26 -07:00
Christopher Celio
e22bf02a80 [commitlog] CSR's cycle optionally set to instret 
- Allows debugging Rocket against Spike by having timer interrupts
    occur in the same place in the instruction stream for both.
 2015-09-15 16:47:26 -07:00
Christopher Celio
7d14abf262 [commitlog] Added privilege-level to output 2015-09-15 16:47:24 -07:00
Christopher Celio
53a02a62c8 [commitlog] Fix sp/dp bug in FPU writeback 2015-09-15 16:46:47 -07:00
Christopher Celio
d630a03857 [commitlog] Added FP instructions to the commitlog 2015-09-15 15:59:13 -07:00
Christopher Celio
91458bef1c [commitlog] Initial commit log for integer working 2015-09-15 15:59:03 -07:00
Christopher Celio
754c47bdd1 Removed "make debug" test from travis 
- currently causes gcc4.8 to crash
  - likely due to high memory requirements in compiling generated c++
    code for debug/vcd output
 2015-09-14 15:45:50 -07:00
Colin Schmidt
d355d81633 regression script bump for new torture that can produce waveforms 2015-09-14 13:00:54 -07:00
Howard Mao
bd536d8832 make HTIFModuleIO an anonymous bundle 2015-09-14 12:58:44 -07:00
Howard Mao
9d89d2a558 get rid of MemIO -> TileLink converters 2015-09-14 12:58:44 -07:00
Howard Mao
f9965648f2 fix up some things in tilelink.scala 2015-09-14 12:57:54 -07:00