Howard Mao
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33f13d5c49
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don't repeat external addr map base
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2016-08-09 21:20:54 -07:00 |
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Howard Mao
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3ea2f4a6c4
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refactor top-level into coreplex and platform
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2016-08-09 18:26:52 -07:00 |
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Howard Mao
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dd1fed41b6
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generate BootROM contents from assembly code
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2016-08-05 16:39:21 -07:00 |
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Howard Mao
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9fa5b228b2
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allow extra devices and top-level ports to be added without changing RocketChip.scala
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2016-08-04 14:06:14 -07:00 |
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Howard Mao
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410e3e5366
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make sure TraceGen gets correct addresses
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2016-08-04 11:08:25 -07:00 |
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Howard Mao
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0a85e92652
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Allow additional internal MMIO devices to be created without changing BaseConfig
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2016-08-04 11:04:52 -07:00 |
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Howard Mao
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f04aefc95c
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get rid of deprecated ZynqAdapter
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2016-08-02 13:14:20 -07:00 |
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Howard Mao
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63b814fcd7
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only run the important (high coverage) tests in regression suite
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2016-08-02 10:54:05 -07:00 |
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Howard Mao
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b7723f1ff8
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make unit tests local to the packages being tested
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2016-08-01 17:02:00 -07:00 |
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Howard Mao
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98eede0505
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some refactoring in RocketChip top-level
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2016-08-01 17:02:00 -07:00 |
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Megan Wachs
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55c992bb3a
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Use FoldRight() instead of for loop
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2016-08-01 16:56:33 -07:00 |
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Megan Wachs
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8db2e8829f
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Allow aggregate CONFIG on Command Line
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2016-08-01 14:24:16 -07:00 |
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Andrew Waterman
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fe670e5421
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Stop using deprecated FileSystemUtilities to create files
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2016-07-31 18:04:56 -07:00 |
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Andrew Waterman
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058396aefe
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[rocket] Implement RVC
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2016-07-29 17:56:42 -07:00 |
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Howard Mao
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cb86aaa46b
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fix trace generator addresses
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2016-07-28 17:56:14 -07:00 |
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Howard Mao
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ecd1af326c
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fix L2 deadlock bug and add more advanced trace generator
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2016-07-26 12:43:08 -07:00 |
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Howard Mao
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1063d90993
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make sure L1 and L2 agree on coherence policy
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2016-07-25 12:20:49 -07:00 |
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Howard Mao
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6a5b2d7f59
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fix assembly tests for configurations without VMU and/or user mode
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2016-07-22 17:21:57 -07:00 |
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Howard Mao
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75347eed56
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some fixes and cleanup to stateless bridge
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2016-07-21 19:51:26 -07:00 |
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Megan Wachs
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c31c650def
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If NTiles == 1, only use MEI. Also Create configuration for ManagerToClientStatelessBridge.
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2016-07-21 13:54:28 -07:00 |
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Howard Mao
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20df74d138
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generate more L1 voluntary releases in TraceGen
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2016-07-21 12:33:55 -07:00 |
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Wesley W. Terpstra
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9ae23f18bd
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rocket: support asynchronous external busses
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2016-07-19 14:52:56 -07:00 |
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Howard Mao
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e08ec42bc0
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refactor groundtest unittests into separate package
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2016-07-16 23:19:55 -07:00 |
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Megan Wachs
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407bc95c42
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Rename MulDivUnroll to MulUnroll
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2016-07-15 15:40:17 -07:00 |
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Megan Wachs
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4c26a6bc96
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Create seperate Mul/Div paramters instead of UseFastMulDiv
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2016-07-15 14:40:37 -07:00 |
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Andrew Waterman
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ba08255450
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bump rocket
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2016-07-14 22:11:19 -07:00 |
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Andrew Waterman
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768403f8fa
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Bump rocket; remove ICacheBufferWays parameter
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2016-07-14 12:50:16 -07:00 |
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Howard Mao
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90bcd3dbdc
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make sure DirectGroundTest testers given correct TL settings
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2016-07-11 18:11:01 -07:00 |
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Howard Mao
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8f0fa11ce4
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optionally export detailed status information in DirectGroundTest
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2016-07-11 18:11:00 -07:00 |
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Howard Mao
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cb2a18b533
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allow direct instatiation of arbitrary non-caching groundtests
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2016-07-11 18:11:00 -07:00 |
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Howard Mao
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f03ffb32a0
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add top that directly tests the TL -> AXI converters
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2016-07-11 18:11:00 -07:00 |
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Howard Mao
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b47f8fbc41
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don't use splat and bug out if too many address map entries
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2016-07-11 18:10:42 -07:00 |
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Wesley W. Terpstra
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46fc9744e2
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rocket: add an AXI master port into the chip
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2016-07-11 12:16:44 -07:00 |
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Wesley W. Terpstra
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8ac7fa5544
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ext: support multiple external AHB/AXI ports
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2016-07-11 12:16:39 -07:00 |
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Howard Mao
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9ec55ebb91
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don't add io:ext region to address map if no external MMIO
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2016-07-08 15:29:35 -07:00 |
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Howard Mao
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35547aa428
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allow NastiConverterTest and Memtest to run simultaneously
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2016-07-08 13:40:52 -07:00 |
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Howard Mao
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358668699f
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refactoring groundtest configuration
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2016-07-08 11:40:16 -07:00 |
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Howard Mao
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eeac405ef8
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get rid of TL -> AXI buffering and fix SimpleHellaCacheIF for non-blocking DCache
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2016-07-08 09:33:07 -07:00 |
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Andrew Waterman
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32ee5432dd
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Fix testing of DefaultSmallConfig; bump rocket et al
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2016-07-07 21:23:49 -07:00 |
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Howard Mao
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8c13e78ab5
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add buffering and locking to TL -> AXI converter
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2016-07-06 16:57:09 -07:00 |
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Howard Mao
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e27cb5f885
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fix voluntary release issue in L2 cache
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2016-07-06 16:57:01 -07:00 |
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Howard Mao
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f79a3285fb
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fix TraceGen and Nasti -> TL converter
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2016-07-05 17:42:57 -07:00 |
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Howard Mao
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c924ec2a22
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fixing bufferless broadcast hub
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2016-07-05 12:10:22 -07:00 |
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Howard Mao
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b01871c3de
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test configurations for both shrinking and growing TL -> MIF
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2016-07-01 18:13:33 -07:00 |
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Howard Mao
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e04e3d2571
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make TestBench generator handle different top module names
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2016-07-01 10:53:08 -07:00 |
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Howard Mao
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600f2da38a
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export TL interface for Mem/MMIO and fix TL width adapters
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2016-06-30 18:20:43 -07:00 |
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Howard Mao
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74cd588c65
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refactor uncore to split into separate packages
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2016-06-28 14:10:25 -07:00 |
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Andrew Waterman
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c725a78086
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Merge RTC into PRCI
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2016-06-27 23:08:29 -07:00 |
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Howard Mao
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d10fc84a8b
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no longer require caching interfaces for groundtest tiles
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2016-06-27 17:32:49 -07:00 |
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Howard Mao
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2dd8d90ae4
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make Comparator fit the GroundTest model
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2016-06-27 16:01:32 -07:00 |
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