riscv/rocket-chip
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99a959e6b18d2d8ffa1e4a2b6a923b55fa6ea118
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Author SHA1 Message Date
Andrew Waterman 99a959e6b1 remove pc+4 piperegs and add new ex pc+4 adder 2012-02-02 13:33:27 -08:00
Andrew Waterman 01a156eb98 make # of dcache lines configurable 2012-02-01 21:11:45 -08:00
Andrew Waterman b1bbf56b74 clean up wb->id bypass 2012-02-01 16:41:18 -08:00
Andrew Waterman 38c9105ea1 fix mul/div deadlock bug 
If independent multiplies or independent divides were issued
back-to-back, the second wouldn't execute, causing the register
to be busy forever.
 2012-01-30 21:14:28 -08:00
Andrew Waterman bd241ea237 fix when badvaddr is set 2012-01-30 17:15:42 -08:00
Andrew Waterman a96c92f58d enable amomin[u]/amomax[u 2012-01-26 20:45:04 -08:00
Andrew Waterman a7999d4525 don't flush I$ unless fence.i commits 
otherwise, we might not make forward progress.
 2012-01-26 20:37:09 -08:00
Andrew Waterman 41855a6d47 fix missing "otherwise" in PCR file 
this fixes timer interrupts for VLSI backend.
 2012-01-26 19:33:55 -08:00
Andrew Waterman 9e6b86fe85 Fix a nasty replay bug 
If a mispredicted branch was followed by an instruction dependent
on a load that missed in the cache, the mispredicted path would
be executed rather than the correct path. Fail.

Example broken code:

lw   x2, 0(x2)          # cache miss
beq  x3, x0, somewhere  # mispredicted branch
move x4, x2             # wrong-path instruction dependent on load miss
 2012-01-24 03:40:01 -08:00
Andrew Waterman 06fdf79dab fix long-latency writeback arbitration bug 2012-01-24 00:56:47 -08:00
Andrew Waterman f1c355e3cd check pc/effective address sign extension 2012-01-24 00:15:17 -08:00
Andrew Waterman a5a020f97b update chisel and remove SRAM_READ_LATENCY 2012-01-23 20:59:38 -08:00
Andrew Waterman e7bf07d55e fix AMO replay bug 2012-01-23 15:35:53 -08:00
Andrew Waterman 31c56228e2 add missing "otherwise" 2012-01-21 20:13:15 -08:00
Andrew Waterman addfe55735 add FPGA memory generator script 2012-01-13 18:19:08 -08:00
Andrew Waterman 20aee36c96 move PCR writes to WB stage 2012-01-02 15:42:39 -08:00
Andrew Waterman 3045b33460 remove second RF write port 
load miss writebacks are treated like mul/div now.
 2012-01-02 02:51:30 -08:00
Andrew Waterman ffe23a1ee8 fix WAW hazard handling 2012-01-02 00:25:11 -08:00
Andrew Waterman eb657dd250 reduce superfluous replays 
we only replay after a cache miss if we mis-scheduled the use of a load.
 2012-01-01 21:28:38 -08:00
Andrew Waterman efc623cc36 validate BTB address and use BTB for J/JAL/JR/JALR 
even if we weren't using the BTB for JR/JALR, we'd need to
flush the BTB on FENCE.I and on context switches, but
validating its result suffices instead.
 2012-01-01 17:04:14 -08:00
Andrew Waterman 2f8fcebea0 remove datapath register resets resets 2012-01-01 16:09:40 -08:00
Andrew Waterman f9160c53cf fixes for correct verilog generation 2011-12-29 23:46:21 -08:00
Andrew Waterman 1028ff7d9b fix multiplier bug 2011-12-29 23:45:09 -08:00
Andrew Waterman d65e1a2eee vlsi verilog compiles now but doesn't simulate 2011-12-20 22:08:27 -08:00
Andrew Waterman 38ea10a5f4 parameterized multiplier unrolling 2011-12-20 04:18:28 -08:00
Andrew Waterman 733fc8e65e booth multiplier 2011-12-20 03:49:07 -08:00
Andrew Waterman b5a8b6dc73 fix divider for RV32 2011-12-19 16:57:53 -08:00
Andrew Waterman bcceb08373 add dummy mul_rdy signal 2011-12-17 07:30:47 -08:00
Andrew Waterman 96c78829b4 improve ALU and fix revealed emulator bug 2011-12-17 07:20:32 -08:00
Andrew Waterman 82700cad72 fix multiplier for rv32 2011-12-17 07:20:00 -08:00
Andrew Waterman a8d0cd95e6 hellacache now works 2011-12-17 03:26:11 -08:00
Andrew Waterman 56c4f44c2a hellacache returns! 
but AMOs are unimplemented.
 2011-12-12 06:49:39 -08:00
Andrew Waterman 8308345364 work in progress on hellacache 2011-12-10 07:01:47 -08:00
Andrew Waterman ce201559f3 Support cache->cpu nacks one cycle after request 2011-12-10 00:42:09 -08:00
Andrew Waterman c01e1f1cef Don't replay from EX stage. 
EX replays are now handled from MEM.  We may move them to WB.
 2011-12-09 19:42:58 -08:00
Andrew Waterman 218f63e66e code cleanup/parameterization 2011-12-09 00:42:43 -08:00
Andrew Waterman a87ad06780 Automatically infer rocketCAM address width 2011-12-06 02:05:40 -08:00
Andrew Waterman 8f3927fdfa queue data type is now templated 2011-11-30 18:08:26 -08:00