The riscv-fesvr submodule was pointing at my local version, oops. This
corrects that in an updated version of riscv-tools.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
* Add +permissive/+permissive-off for VCS args
This adds guards around Verilog/VCS options for VCS calls with HTIF's
new `+permissive`/`+permissive-off` options. This enables HTIF to
permissively parse all options inside one of these guards while not
erroring on unknonw commands. This is necessary for VCS, unlike with the
emulator, as HTIF is giving all commands as opposed to only host and
target arguments (like with Verilator/emulator.cc).
* Bump riscv-tools for fesvr VCS fix
* Bump riscv-rools/riscv-fesvr (VCS stderr fix)
Fixes#1266
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
AMO.aq should be implemented as AMO;FENCE, whereas AMO.rl should be
implemented as FENCE;AMO. These had been swapped. This error does
not affect cacheable accesses using the blocking D$, nor does it
affect accesses to the data scratchpad, nor does it affect accesses
to strongly ordered I/O regions (which is the default).
Cacheable accesses using the nonblocking D$ and accesses to weakly
ordered I/O regions may manifest memory-ordering violations. For
these accesses, the workaround is to use AMO.aqrl whenever AMO.aq
or AMO.rl had been used.
This proposal hasn't been adopted yet, but anything is better than the
current implementation, where clearing misa.C when the PC is misaligned
is effectively undefined.
In Rocket, debug triggers are supposed to happen before a store
occurs, rather than after. Previously, we reported the exception
on the store's PC, but the store occurred anyway. This probably
hasn't been problematic in practice because most stores are
idempotent.
