Andrew Waterman
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31f0b600fd
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add dessert
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2012-03-25 23:03:20 -07:00 |
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Andrew Waterman
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5a00143035
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loop host.in to host.out during reset
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2012-03-25 21:45:10 -07:00 |
|
Andrew Waterman
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1666d3fbd7
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loop host.in to host.out during reset
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2012-03-25 21:45:10 -07:00 |
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Andrew Waterman
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f62a02ab54
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remove dumb stuff in top.scala
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2012-03-25 21:30:01 -07:00 |
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Andrew Waterman
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a7ebea13fc
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add mem serdes unit
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2012-03-25 17:03:58 -07:00 |
|
Andrew Waterman
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88bf8a4f23
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add mem serdes unit
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2012-03-25 17:03:58 -07:00 |
|
Andrew Waterman
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7fa93da4f5
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add backup memory port (disabled for now)
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2012-03-25 15:49:32 -07:00 |
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Yunsup Lee
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1f33f6bb58
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HAVE_VEC is on
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2012-03-24 20:54:43 -07:00 |
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Andrew Waterman
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86d56ff67b
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refactor cpu/i$/d$ into Tile (rather than Top)
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2012-03-24 16:57:28 -07:00 |
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Andrew Waterman
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3a487ac89b
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improve htif<->pcr interface
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2012-03-24 16:57:28 -07:00 |
|
Andrew Waterman
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54fa6f660d
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new supervisor mode
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2012-03-24 13:03:31 -07:00 |
|
Yunsup Lee
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65929a62e3
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fix reset value for appvl
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2012-03-22 15:32:04 -07:00 |
|
Yunsup Lee
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aaed0241af
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get rid of vxcptwait
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2012-03-21 15:09:04 -07:00 |
|
Yunsup Lee
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023734175d
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now fence stalls in decode
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2012-03-20 17:10:05 -07:00 |
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Yunsup Lee
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e450e3aa40
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fix irt counter bug regarding vector stuff
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2012-03-20 17:09:54 -07:00 |
|
Yunsup Lee
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7d7d7f49f9
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change the tlb arbiter to a round robing one
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2012-03-20 15:21:36 -07:00 |
|
Yunsup Lee
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5f69c5a764
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fix bug in coherence hub, specifically in abort handling logic
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2012-03-20 02:16:28 -07:00 |
|
Yunsup Lee
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1cddd5de56
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fix amo locking up problem
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2012-03-20 02:16:28 -07:00 |
|
Yunsup Lee
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56cb9b7a63
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fix bug in coherence hub, specifically in abort handling logic
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2012-03-20 02:16:28 -07:00 |
|
Yunsup Lee
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c036fff79c
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fix id interrupt signal
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2012-03-19 15:13:57 -07:00 |
|
Yunsup Lee
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0edea00166
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now HAVE_VEC is true, since it passes the emulator
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2012-03-19 03:10:00 -07:00 |
|
Yunsup Lee
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264732556f
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fixes to match verilog X semantics
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2012-03-19 03:10:00 -07:00 |
|
Andrew Waterman
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bd27d0fab2
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can now take interrupts on stalled instructions
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2012-03-19 01:02:06 -07:00 |
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Andrew Waterman
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2ed0be65f9
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fix RRArbiter
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2012-03-19 00:19:33 -07:00 |
|
Yunsup Lee
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ba06cd953e
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add chosen
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2012-03-18 20:43:17 -07:00 |
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Andrew Waterman
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c4a91303fb
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update vector fence names and encoding
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2012-03-18 20:42:38 -07:00 |
|
Yunsup Lee
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2a01f558ba
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fix unmasked valid bug in ctrl_vec
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2012-03-18 19:55:24 -07:00 |
|
Yunsup Lee
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98e10ddc3c
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update vector exception instructions
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2012-03-18 16:36:12 -07:00 |
|
Yunsup Lee
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7493d55d3f
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add pf fault handling
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2012-03-18 15:06:39 -07:00 |
|
Yunsup Lee
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62ada5ea9e
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hookup vitlb ptw port
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2012-03-17 23:01:06 -07:00 |
|
Yunsup Lee
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b793d63182
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no vector interrupt masking
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2012-03-17 23:01:06 -07:00 |
|
Yunsup Lee
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8a4f95e617
|
changes to xcpt handling
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2012-03-17 17:50:37 -07:00 |
|
Yunsup Lee
|
8c50c81b81
|
drop vec_irq_aux pcr register, now everything goes through badvaddr
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2012-03-17 14:03:57 -07:00 |
|
Yunsup Lee
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3b4680a834
|
add vitlb exception port
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2012-03-17 14:03:33 -07:00 |
|
Andrew Waterman
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a47eeb9571
|
retime D$ bypass into beginning of EX stage
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2012-03-16 18:35:54 -07:00 |
|
Andrew Waterman
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6c26921766
|
reduce D$ critical path through page table walker
costs an extra cycle per page table level to resolve a TLB miss. too bad.
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2012-03-16 18:35:54 -07:00 |
|
Yunsup Lee
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d38603a4ee
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change number of tlb entries
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2012-03-16 17:08:03 -07:00 |
|
Andrew Waterman
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e38114e4b0
|
fix coherence bug
popping wrong store dependence queue
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2012-03-16 01:24:07 -07:00 |
|
Andrew Waterman
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f0157b9e2a
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fix coherence bug
popping wrong store dependence queue
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2012-03-16 01:24:07 -07:00 |
|
Andrew Waterman
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cfca2d1411
|
clean up cache interfaces; avoid reserved keywords
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2012-03-16 00:44:16 -07:00 |
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Andrew Waterman
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820884c7e6
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fix probes for smaller cache sizes
address bits (pgidx_bits-1,taglsb) were omitted from tag checks.
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2012-03-15 23:08:30 -07:00 |
|
Andrew Waterman
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4684171ac6
|
fix fence.i for associative caches
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2012-03-15 21:23:21 -07:00 |
|
Andrew Waterman
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3129040bda
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use divided clk for htif. UDPATE YOUR FESVR
by default, we now load programs via a backdoor, because otherwise
it takes too long to simulate.
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2012-03-15 18:36:51 -07:00 |
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Andrew Waterman
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2b0bc8df2b
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use divided clk for htif. UDPATE YOUR FESVR
by default, we now load programs via a backdoor, because otherwise
it takes too long to simulate.
|
2012-03-15 18:36:51 -07:00 |
|
Yunsup Lee
|
ba566f246e
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change icache parameters
|
2012-03-15 15:35:12 -07:00 |
|
Yunsup Lee
|
72006160dc
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fix vxcptwait inst bug, it was incorrect when exception_valid was on before do_xcptwait
|
2012-03-15 02:10:21 -07:00 |
|
Yunsup Lee
|
f972977da1
|
refactored VMU, now uses one skid buffer
|
2012-03-15 01:10:17 -07:00 |
|
Henry Cook
|
b5fa86e844
|
4-way associative by default
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2012-03-14 17:51:12 -07:00 |
|
Andrew Waterman
|
77c405ffa1
|
use broadcast hub and coherent HTIF
|
2012-03-14 16:44:35 -07:00 |
|
Andrew Waterman
|
7dde7099d2
|
use broadcast hub and coherent HTIF
|
2012-03-14 16:44:35 -07:00 |
|