riscv/rocket-chip
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Author SHA1 Message Date
Andrew Waterman
a999c055ed Don't take an interrupt when EX stage PC is invalid 
It was possible to take an interrupt on the instruction in the shadow of
a short forward branch.  EPC would thus get the wrong value, and so
a wrong-path instruction would be executed upon return from interrupt.

h/t Yunsup
 2014-09-11 01:46:52 -07:00
Yunsup Lee
02c08a156f generate consts.vh from chisel source 2014-09-10 17:14:55 -07:00
Yunsup Lee
cfecd8832d tease out reference-chip specific stuff 2014-09-09 20:49:28 -07:00
Yunsup Lee
6b6bdd2b83 decommission Slave top-level module for fpga build 2014-09-08 00:23:15 -07:00
Yunsup Lee
ddfd3ce968 further generalize fpga/vlsi builds 2014-09-08 00:21:57 -07:00
Yunsup Lee
3175a40509 add berkeley-hardfloat as submodule 2014-09-08 00:18:49 -07:00
Yunsup Lee
1e5b2f658f remove existing hardfloat repository 2014-09-07 23:45:47 -07:00
Henry Cook
ae05125f29 Adjustements to top-level parameters and knobs for hwacha 2014-09-07 17:57:33 -07:00
Henry Cook
5eb5e9eaf5 Standardize ()=>Module(...) top-level Parameters 2014-09-07 17:54:41 -07:00
Henry Cook
4126678c9d Merge branch 'dse' 
Conflicts:
	rocket
	uncore
 2014-09-06 06:59:14 -07:00
Henry Cook
5e26b4ab66 Merge branch 'dse' 
Conflicts:
	src/main/scala/htif.scala
	src/main/scala/llc.scala
 2014-09-06 06:16:58 -07:00
Henry Cook
5e2f98747f Merge branch 'dse' 2014-09-06 06:10:15 -07:00
Yunsup Lee
1cb2d1d7b7 initialize all SRAMs to avoid X propagation problem 2014-09-04 11:06:01 -07:00
Yunsup Lee
763c57931b fix problem introduced with verilog generation in vsim/fsim 2014-09-04 09:49:57 -07:00
Scott Beamer
6c6f5a3843 add verilog target to build without simulator 2014-09-03 17:28:45 -07:00
Scott Beamer
13b6ec4712 including better sbt fixes 2014-09-02 15:16:31 -07:00
Scott Beamer
f8821b4cc9 better fix with explanation of sbt issue 2014-09-02 15:16:03 -07:00
Scott Beamer
600c5d50a9 better fix with explanation of sbt issue 2014-09-02 15:14:56 -07:00
Scott Beamer
26649b30ed fixes sbt error during first run 2014-09-02 14:34:55 -07:00
Scott Beamer
f9922a106b fixes sbt error during first run 2014-09-02 14:34:36 -07:00
Scott Beamer
bfb662968d fixes sbt error during first run 2014-09-02 14:33:58 -07:00
Henry Cook
82467313dd merge in rocketchip changes from master 2014-09-02 13:51:57 -07:00
Henry Cook
3250db0dd5 bump uncore 2014-09-02 12:37:44 -07:00
Henry Cook
712f3a754d merge in master 2014-09-02 12:34:42 -07:00
Henry Cook
8622eb0f5b bump rocket 2014-09-01 13:34:15 -07:00
Henry Cook
b42a2ab40a Final parameter refactor 2014-09-01 13:28:58 -07:00
Adam Izraelevitz
2d6aafc32e Merge branch 'dse' of github.com:ucb-bar/rocket-staging into HEAD 2014-09-01 11:23:50 -07:00
Yunsup Lee
7734285507 forgot to comment out hwacha 2014-09-01 09:01:36 -07:00
Yunsup Lee
0d18e491c7 update gitignore 2014-09-01 08:59:59 -07:00
Yunsup Lee
882fecf43a update README 2014-08-31 20:57:16 -07:00
Yunsup Lee
c03c09ec31 update for rocket-chip release 2014-08-31 20:26:55 -07:00
Sagar Karandikar
83c6c2c9e2 rename refs to zynq-fpga to fpga-zynq 2014-08-29 10:26:48 -07:00
Henry Cook
78ab83d224 refactor fpga top/config 2014-08-28 13:07:54 -07:00
Scott Beamer
83380053de use fpga backend for fpga 2014-08-26 15:56:27 -07:00
Henry Cook
bf356b9cb4 Refactor to combine fpga and vlsi tops, part 1 2014-08-24 19:30:53 -07:00
Henry Cook
17b2359c9a htif parameters trait 2014-08-24 19:27:58 -07:00
Henry Cook
a41d55b643 Final parameter refactor. 2014-08-23 01:26:03 -07:00
Henry Cook
dc5643b12f Final parameter refactor. 2014-08-23 01:19:36 -07:00
Scott Beamer
63b62394d9 added l2 to fpga 
with new chisel & uncore, it goes into brams
 2014-08-20 15:41:07 -07:00
Scott Beamer
e384b33cc3 don't generate a write mask for BigMem if it isn't used 
not needed for llc data
 2014-08-19 15:50:20 -07:00
Henry Cook
9b36162b67 Point rocket/ to rocket-staging repo 2014-08-19 14:20:15 -07:00
Henry Cook
2741bbf2b9 Point rocket/ to rocket-staging repo 2014-08-19 13:53:24 -07:00
Henry Cook
6a4193cf90 minor cache param cleanup 2014-08-19 11:38:46 -07:00
Henry Cook
2de268b3b1 Cache utility traits. Completely compiles, asm tests hang. 2014-08-19 11:38:20 -07:00
Henry Cook
ca5f38ff26 a few more fixes. some param lookups fail (here() in Alter blocks) 2014-08-19 11:38:11 -07:00
Henry Cook
0dac9a7467 Full conversion to params. Compiles but does not elaborate. 2014-08-19 11:38:02 -07:00
Adam Izraelevitz
4e6d69892d Added initial brainstorm for parameter hierarchical flattening, does not compile ;) 2014-08-19 11:37:50 -07:00
Adam Izraelevitz
812353bace Ported FPU parameters to new Chisel Parameters 2014-08-19 11:37:27 -07:00
Yunsup Lee
4ac8e59b1f add .gitignore 2014-08-18 19:27:50 -07:00
Yunsup Lee
d520846638 add README and sbt files 2014-08-18 19:23:10 -07:00