Andrew Waterman
|
0d124d283a
|
Write our own vcs main() routine
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2014-03-17 17:02:28 -07:00 |
|
Andrew Waterman
|
7f23257873
|
Print out random seed if test fails
|
2014-03-17 15:35:32 -07:00 |
|
Andrew Waterman
|
fcbbb275aa
|
Fix nondeterminism
|
2014-03-15 17:35:30 -07:00 |
|
Andrew Waterman
|
54cbf0c4f1
|
Add (unused) RV32 CSRs
|
2014-03-15 17:33:17 -07:00 |
|
Andrew Waterman
|
943d7ac80a
|
Use LinkedHashSet/Map for simpler determinism
|
2014-03-15 17:31:48 -07:00 |
|
Donggyu Kim
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53d62cb69d
|
remove nondeterminism
|
2014-03-15 16:45:58 -07:00 |
|
Yunsup Lee
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e4b56b5d0e
|
generate verilog for rekall
|
2014-03-15 15:31:04 -07:00 |
|
Andrew Waterman
|
b6bf7cfe0c
|
push chisel
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2014-03-11 23:56:57 -07:00 |
|
Andrew Waterman
|
7ac003a4f7
|
push hardfloat
|
2014-03-11 20:36:39 -07:00 |
|
Andrew Waterman
|
f04bde75fb
|
New FP encoding
|
2014-03-11 19:12:20 -07:00 |
|
Andrew Waterman
|
a0389645b7
|
New FP encoding; improved FP implementation
|
2014-03-11 18:58:24 -07:00 |
|
Andrew Waterman
|
00bc1a2293
|
Add fclass.{s|d} instructions
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2014-03-10 16:59:24 -07:00 |
|
Yunsup Lee
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6951333a08
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push rocket
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2014-03-04 23:43:00 -08:00 |
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Yunsup Lee
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ac4b3f9f22
|
print out core id
|
2014-03-04 23:38:49 -08:00 |
|
Andrew Waterman
|
d055c0ebaf
|
Push rocket/hardfloat/chisel
|
2014-03-04 16:39:06 -08:00 |
|
Andrew Waterman
|
9f2e16c58a
|
Fix D$ arbiter for >2 inputs
|
2014-03-04 16:32:17 -08:00 |
|
Andrew Waterman
|
fa75f6e81e
|
Fix null pointer exception when HAS_FPU=false
|
2014-03-04 16:32:09 -08:00 |
|
Yunsup Lee
|
23045ec379
|
add hwacha vfmsv instructions, keepcfg bug fix, turn off secondary fconv
|
2014-03-02 03:38:06 -08:00 |
|
Yunsup Lee
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49f0e43ed1
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push riscv-tools
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2014-03-01 03:31:03 -08:00 |
|
Yunsup Lee
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e20d50436a
|
committed in the wrong directory, meant to commit in the hwacha directory
|
2014-03-01 00:01:35 -08:00 |
|
Yunsup Lee
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8c459df3b6
|
flush deck when xcpt occurs, fixes remaining p test bugs
|
2014-02-28 22:50:34 -08:00 |
|
Adam Izraelevitz
|
cb14baab88
|
Reformatted hammer directory, added parent scripts to repo, as well as README.
|
2014-02-28 15:57:46 -08:00 |
|
Andrew Waterman
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c7110c8389
|
Make FPU pipeline depths configurable
|
2014-02-28 13:39:59 -08:00 |
|
Yunsup Lee
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0c4442c172
|
push tests/tools
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2014-02-27 20:28:19 -08:00 |
|
Yunsup Lee
|
bcfcdefe88
|
update hwacha
|
2014-02-27 04:39:12 -08:00 |
|
Yunsup Lee
|
46714c0c60
|
more improvements to hwacha
|
2014-02-26 21:20:53 -08:00 |
|
Yunsup Lee
|
a5625de3d5
|
support vector irq tests
|
2014-02-25 21:18:03 -08:00 |
|
Ben Keller
|
fcfc1078f8
|
Merge branch 'master' of github.com:ucb-bar/reference-chip
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2014-02-25 15:54:19 -08:00 |
|
Yunsup Lee
|
220076506c
|
push hwacha; all vector p/v/pt tests work now
|
2014-02-25 03:51:15 -08:00 |
|
Yunsup Lee
|
e5c2bd5e7b
|
add extensions option to riscv-dis for better disassembly
|
2014-02-25 03:50:32 -08:00 |
|
Yunsup Lee
|
98b830201a
|
add wen signal to dasm printf
|
2014-02-25 03:31:06 -08:00 |
|
Yunsup Lee
|
8acc9510c4
|
push hwacha,chisel
|
2014-02-24 01:43:55 -08:00 |
|
Yunsup Lee
|
22345dd073
|
push rocket,hwacha
|
2014-02-22 22:53:24 -08:00 |
|
Yunsup Lee
|
97b1841fcf
|
change dcache tag bits to 7
|
2014-02-22 22:53:04 -08:00 |
|
Adam Izraelevitz
|
f14f386b4f
|
Merge branch 'dse' of github.com:ucb-bar/reference-chip into dse
Conflicts:
src/main/scala/ReferenceChip.scala
|
2014-02-19 15:50:28 -08:00 |
|
Adam Izraelevitz
|
a006bffca4
|
Merge branch 'master' of github.com:ucb-bar/reference-chip into dse
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2014-02-19 15:04:03 -08:00 |
|
Adam Izraelevitz
|
58d2e62e3f
|
Merge branch 'master' of github.com:ucb-bar/reference-chip into dse
Conflicts:
chisel
src/main/scala/ReferenceChip.scala
|
2014-02-19 14:24:36 -08:00 |
|
Andrew Waterman
|
de965d558a
|
Renumber uarch CSRs into custom CSR space
|
2014-02-14 17:41:17 -08:00 |
|
Andrew Waterman
|
e554f6728d
|
Update chisel
|
2014-02-14 17:41:17 -08:00 |
|
Andrew Waterman
|
8e3ca609f7
|
Renumber uarch CSRs into custom CSR space
|
2014-02-14 17:40:00 -08:00 |
|
Stephen Twigg
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755293d785
|
Push hwacha (refactoring) and add line that when uncommented properly instantiates hwacha).
|
2014-02-14 10:12:09 -08:00 |
|
Andrew Waterman
|
02dbd6b0aa
|
Don't assign to your own inputs
|
2014-02-12 18:39:40 -08:00 |
|
Stephen Twigg
|
6808245bb5
|
Timeout cycles now defined in toplevel Makefrag in order to allow for easier alteration when debugging.
|
2014-02-12 16:50:13 -08:00 |
|
Andrew Waterman
|
e5de170215
|
Update Chisel, fixing Verilog backend
|
2014-02-12 14:28:43 -08:00 |
|
Adam Izraelevitz
|
e25c54e998
|
Merge branch 'dse' of github.com:ucb-bar/reference-chip into dse
|
2014-02-12 13:52:24 -08:00 |
|
Adam Izraelevitz
|
c1e544886f
|
Merge branch 'dse' of github.com:ucb-bar/reference-chip into dse
|
2014-02-12 13:35:12 -08:00 |
|
Adam Izraelevitz
|
1a03a64572
|
Merge branch 'dse' of github.com:ucb-bar/reference-chip into dse
|
2014-02-12 12:44:30 -08:00 |
|
Adam Izraelevitz
|
aae5f465c1
|
Merge branch 'master' of github.com:ucb-bar/reference-chip into dse
Conflicts:
src/main/scala/ReferenceChip.scala
|
2014-02-11 17:31:55 -08:00 |
|
Adam Izraelevitz
|
548cf16061
|
Added jack Makefile and hammer.scala, as well as changed reference chip to have multiple datacache sizes. Requires chisel branch dse
|
2014-02-11 14:36:47 -08:00 |
|
Andrew Waterman
|
0ebb115a3c
|
Revert to old AUIPC definition
|
2014-02-10 19:05:14 -08:00 |
|