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2014-02-14 10:12:09 -08:00
chisel@0bbe5010d8 Update Chisel, fixing Verilog backend 2014-02-12 14:28:43 -08:00
csrc Linux works again! 2014-01-16 12:44:29 -08:00
dramsim2@0b3ee6799a integrate updated rocket/uncore 2012-10-18 17:51:41 -07:00
emulator Timeout cycles now defined in toplevel Makefrag in order to allow for easier alteration when debugging. 2014-02-12 16:50:13 -08:00
hardfloat@d126925915 Fix tests when !hwacha; disable hwacha by default 2014-02-06 03:08:33 -08:00
project allow chisel to elaborate Modules outside of the ReferenceChip package 2014-02-05 03:29:23 -08:00
riscv-tests@c50db79a8e Revert to old AUIPC definition 2014-02-10 19:05:14 -08:00
riscv-tools@9a2d419bc3 Revert to old AUIPC definition 2014-02-10 19:05:14 -08:00
rocket@3fd053615e Revert to old AUIPC definition 2014-02-10 19:05:14 -08:00
src/main/scala Push hwacha (refactoring) and add line that when uncommented properly instantiates hwacha). 2014-02-14 10:12:09 -08:00
uncore@f2a0b435fd cleanups supporting uncore hierarchy 2014-01-31 16:03:58 -08:00
.gitignore Properly ignore target files. Push uncore (properly ignore target files) 2013-09-24 16:03:28 -07:00
.gitmodules add chisel and hardfloat back as sub-projects, bump other sub-projects 2013-09-26 12:01:46 -07:00
Makefrag Timeout cycles now defined in toplevel Makefrag in order to allow for easier alteration when debugging. 2014-02-12 16:50:13 -08:00
README use --recursive to populate all submodules. with current instructions you can't run tests because riscv-tests/env isn't pulled in 2014-02-06 16:20:48 -08:00
sbt-launch.jar Bump scala to 2.10.2, sbt to 0.13-RC2, including new launcher. Upgrade reflection in network.scala to 2.10 lib. Constants now obtained from subproject package objects. Give network its own file. 2013-07-24 23:28:43 -07:00

Quick and dirty instructions:

CHECKOUT THE CODE:

  git submodule update --init --recursive


BUILDING THE TOOLCHAIN:

  To build RISC-V ISA simulator, frontend server, proxy kernel and newlib based GNU toolchain:

    export RISCV=/path/to/riscv/toolchain/installation
    cd riscv-tools
    ./build.sh

  To build asm tests and benchmarks (you must have the RISC-V toolchain installed and in your path):

    cd riscv-tests/isa/
    make -j

    cd riscv-tests/benchmarks
    make -j

BUILDING THE PROJECT:

  To build the C simulator:

    cd emulator
    make

  To build the VCS simulator:

    cd vlsi/build/vcs-sim-rtl
    make

  in either case, you can run a set of assembly tests or simple benchmarks:

    make run-asm-tests
    make run-vecasm-tests
    make run-vecasm-timer-tests
    make run-bmarks-test

  To build a C simulator that is capable of VCD waveform generation:

    cd emulator
    make emulator-debug

  And to run the assembly tests on the C simulator and generate waveforms:

    make run-asm-tests-debug
    make run-vecasm-tests-debug
    make run-vecasm-timer-tests-debug
    make run-bmarks-test-debug


UPDATING TO A NEWER VERSION OF CHISEL:

  To grab a newer version of chisel:

    git submodule update --init
    cd chisel
    git pull origin master

  Then, to compile it and install it into the rocket repo:

    cd sbt
    sbt package
    cp chisel/target/scala-2.8.1/chisel_2.8.1-1.1.jar ../../sbt/work/lib

  If you commit a new jar, you must also commit the updated chisel submodule.