riscv/rocket-chip
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Author SHA1 Message Date
Andrew Waterman f0a0687589 bump tools for .align 2 fix in riscv-tests 2017-11-11 19:13:59 -08:00
Andrew Waterman 4ebca73d59 Provide option to support AMOs only on I/O, not DTIM/D$ 2017-11-09 17:45:53 -08:00
Andrew Waterman d0c6cbba6b Improve frontend branch prediction 
- Put correctness responsibility on Frontend, not IBuf, for improved
  separation of concerns.  Frontend must detect case that the BTB
  predicts a taken branch in the middle of an instruction.

- Pass BTB information down pipeline unconditionally, fixing case that
  screws up the branch history when the BTB misses and the instruction
  is misaligned.

- Remove jumpInFrontend option; it's now unconditional.

- Default to one-bit counters in the BHT.  For tiny BHTs like these, it's
  more resource efficient to have a larger index space than to have
  hysteresis.
 2017-11-09 00:00:56 -08:00
Andrew WatermanandWesley W. Terpstra bb9d8264e2 "Correct" ITIM uncorrectable errors 
This permits forward progress when a core wants to handle its own
uncorrectable ITIM errors.  Previously, another core had to do it.
 2017-11-08 22:15:03 -08:00
Andrew WatermanandWesley W. Terpstra 5c1b34d854 Don't report a TL error if overwriting a whole ITIM word 2017-11-08 22:15:03 -08:00
Andrew WatermanandWesley W. Terpstra 9b16d25861 Fix reporting of ITIM error addresses on slave-port accesses 2017-11-08 22:15:03 -08:00
Andrew Waterman 34f38b0fb1 Don't permit vectoring of high interrupts 
Send them to the base of the vector to obviate an adder
 2017-11-07 01:59:30 -08:00
Andrew Waterman 6176b348dc Invalidate TL error bit in D$ once progress is made 2017-11-07 00:52:18 -08:00
Andrew Waterman d8d4504995 Provide separate masks for local & global BusErrorUnit interrupts 2017-11-06 18:03:59 -08:00
Andrew Waterman be3a3e0187 Generate local interrupt #128 on bus errors 
It doesn't have a correpsonding bit in mip/mie, so it isn't individually
maskable, nor is it delegable.
 2017-11-06 18:03:59 -08:00
Andrew Waterman ac096a89e7 Make BusErrorUnit support 32-bit stores 
Otherwise it isn't too useful for RV32!
 2017-11-06 18:03:59 -08:00
Andrew Waterman 6357db0b12 Expose BusErrorUnit non-diplomatically for use as local interrupt 2017-11-06 18:03:59 -08:00
Andrew Waterman 95d00b13cc Report ITIM slave port errors to BusErrorUnit 2017-11-06 12:39:17 -08:00
Andrew Waterman c84848afa6 Report ITIM uncorrectable errors over D-channel 2017-11-06 12:32:45 -08:00
Andrew Waterman 989eeb78f9 Prevent some unnecessary pipeline replays 2017-11-06 11:04:06 -08:00
Andrew Waterman c8bc487ab8 Use pseudo-LRU policy in BTB 
FIFO falls on its face if the working set doesn't fit in the BTB.
 2017-11-03 16:27:04 -07:00
Andrew Waterman f859da85ff Disable covers that don't apply to DTIM 2017-11-03 15:38:13 -07:00
Andrew Waterman d6ede818ee DTIM doesn't accept grants 2017-11-03 15:37:48 -07:00
Andrew Waterman a2b80100e2 Make PseudoLRU policy support non-power-of-2 sizes 2017-11-01 01:47:23 -07:00
Andrew Waterman 1474ab438d Remove extraneous signal 2017-10-09 18:33:50 -07:00
Andrew Waterman f3825270c1 Add some covers for L1 memory system 2017-10-09 18:33:36 -07:00
Andrew Waterman 2c4009a138 Fix paddrBits < xLen && paddrBits == vaddrBits case 
Require and/or force vaddrBits to be bigger than paddrBits so there's
room to zero-extend a physical address by 1 bit, so that when the virtual
address is sign-extended, the sign is zero.
 2017-10-09 16:48:04 -07:00
Andrew Waterman 986cbfb6b1 For Rockets without VM, widen vaddrBits to paddrBits 
This supports addressing a >39-bit physical address space.
 2017-10-08 01:21:47 -07:00
Andrew Waterman a0e5a20b60 Don't route branch comparison result through ALU output mux 
This potentially mitigates a critical path, and makes the ALU usable
in processors that have dedicated branch comparators.
 2017-10-07 17:36:24 -07:00
Andrew Waterman 36c39d01e4 Factor out most of HasRocketTiles into HasTiles 2017-10-07 17:36:24 -07:00
Andrew Waterman 70a4127cb8 Factor out some of HaveRocketTiles into HaveTiles 2017-10-07 17:36:24 -07:00
Andrew Waterman 34e96c03b1 Move HCF to BaseTile 2017-10-07 17:36:24 -07:00
Andrew Waterman 71205b70cc Make RocketTileWrapper a BaseTile 2017-10-07 17:36:24 -07:00
Andrew Waterman 4645b61fd3 Decouple BaseTile from HasTileLinkMasterPort 2017-10-07 17:36:24 -07:00
Andrew Waterman 7bcf28c585 Define fetchBytes in HasCoreParams, not Frontend 
It is more generally useful.
 2017-10-03 17:34:18 -07:00
Andrew Waterman 2786e42d99 Don't register interrupts in CSRFile 
They are usually registered outside the tile in a CDC.
 2017-10-03 17:34:18 -07:00
Andrew Waterman 5cfe070932 Add option to make misa read-only 2017-10-03 17:34:18 -07:00
Andrew Waterman 09468a272b Add option to remove basic counters (mcycle/minstret) 2017-10-03 17:34:18 -07:00
Andrew Waterman ab0821f25b Move microarchitecture-neutral params from Rocket to Core 
This makes some of the units more reusable.
 2017-10-03 17:34:18 -07:00
Andrew Waterman 190d5c50d9 Remove deprecated custom-CSR support 2017-10-03 17:34:18 -07:00
Andrew Waterman 9eaf50762e Don't report exceptions as valid instructions in the printed log 2017-09-27 16:29:42 -07:00
Andrew Waterman 31c5246446 Provide correct trace insn on interrupts when possible 2017-09-27 16:27:53 -07:00
Andrew Waterman 78f3877e02 Trace tval field should be zero when not taking exceptions 2017-09-27 12:51:10 -07:00
Andrew Waterman 583adeee88 Separate interrupt bit from cause field in trace bundle 2017-09-27 12:41:30 -07:00
Andrew Waterman 88c782cc70 Report D$ uncorrectable errors on C channel 2017-09-20 17:15:11 -07:00
Andrew Waterman 6bc20942b5 Don't cache TL error responses; report access exceptions 2017-09-20 17:01:08 -07:00
Andrew Waterman 9b828a2640 Only look at error signal on last beat 2017-09-20 15:15:21 -07:00
Andrew Waterman 026fa14bf8 Rename trace.addr -> iaddr 2017-09-20 14:32:41 -07:00
Andrew Waterman f5bd639863 Don't write badaddr on misaligned fetch exceptions 
It's optional, and we were doing it wrong before, so just don't do it.
 2017-09-20 10:52:41 -07:00
Andrew Waterman db57e943f3 Report TL errors into D$ 2017-09-20 00:05:07 -07:00
Andrew Waterman aaad73f019 Add an intra-tile xbar 2017-09-20 00:05:07 -07:00
Andrew Waterman afad25fceb Integrate L1 BusErrorUnit 2017-09-20 00:05:07 -07:00
Andrew Waterman dbf599f6a1 Support SynchronizerShiftReg(sync = 0) 
This makes it easier to parameterize code where the synchronizer
might not always be needed.
 2017-09-20 00:05:07 -07:00
Andrew Waterman 79dab487fc Implement bus error unit 2017-09-20 00:05:07 -07:00
Andrew Waterman ed18acaae0 Report D$ errors 2017-09-20 00:05:07 -07:00
Andrew Waterman 034ea722f4 Report I$ errors 2017-09-20 00:05:07 -07:00
Andrew Waterman 9a175b0fb1 Statically report error correction/detection capability from ECC codes 2017-09-20 00:05:07 -07:00
Andrew Waterman 4d6d6ff641 Add instruction-trace port 2017-09-19 22:59:57 -07:00
Andrew Waterman 87b92cb206 Scan AddressDecoder bits left to right 
This heuristic is brittle but fixes deduplication in RocketTile.
 2017-09-19 17:47:24 -07:00
Andrew Waterman 72bd89a2af Add another AddressDecoder debug message 2017-09-19 17:47:17 -07:00
Andrew Waterman fb2ad11347 Improve AddressDecoder optimization function 
This function is better 27% of the time but worse 6% of the time.
 2017-09-19 17:47:12 -07:00
Andrew Waterman d93d7b9fa4 Only merge stores that aren't yet pending 
This fixes a deadlock (and possibly memory corruption, though that is
unconfirmed).  The following sequence manifests it, assuming t0
is 32-byte aligned:

    sw t0, 0(t0)
    sw t0, 16(t0)
    lw t1, 4(t0)
    lw t2, 4(t0)
 2017-09-17 15:01:07 -07:00
Andrew Waterman 8087a205cc Remove redundant check in interrupt priority encoding 
chooseInterrupts already sorts M interrupts above S interrupts.
 2017-08-17 22:23:42 -07:00
Andrew Waterman cbe7c51b50 Respect ISA requirements on interrupt priority order 
https://github.com/riscv/riscv-isa-manual/commit/a62e76cb16eb508199f74632eb8bf263739f25a3
 2017-08-17 21:27:08 -07:00
Andrew Waterman 3cbc5262ec Don't permit new acquires until the release queue is drained 
If the queue is not empty before a dirty miss, C could block D.
I haven't seen this in the wild, but it could happen because of
dirty probe responses backed up in the queue.
 2017-08-13 13:18:45 -07:00
Andrew Waterman 0190724492 Actually use the C-channel acquire-before-release queue 
oops...
 2017-08-13 13:03:35 -07:00
Andrew Waterman 7387f2a93a Don't block D-channel when handling a probe 
This is an acquire-before-release regression.
 2017-08-12 16:13:24 -07:00
Andrew Waterman 604abd5b07 Only report ECC errors when the RAM was actually read 2017-08-12 15:28:03 -07:00
Andrew Waterman 18fb052fc9 DRY 2017-08-12 15:27:30 -07:00
Andrew Waterman 176110b6d3 Don't trigger ECC writebacks when a release is in flight 2017-08-12 15:23:57 -07:00
Andrew WatermanandYunsup Lee 721770244e Fix IBuf bug 
Don't examine a packet's xcpt signal if it might be invalid.  In this case,
the correct fix is to not examine xcpt at all; the deleted code was vestigial.
(Note, the other use of xcpt(j+1) in this code is indeed safe.)
 2017-08-09 09:47:51 -07:00
Andrew Waterman 31b75987ca Avoid width warning 2017-08-08 20:57:31 -07:00
Andrew Waterman 809c7e8551 Don't merge stores that manifest WAW hazards 
The following sequence would drop the first store when eccBytes=4:

    sb x0, 0(t0)
    nop
    sb x0, 4(t0)
    nop
    sb x0, 1(t0)

Because the first and second store are to different ECC granules, the
hazard check correctly allowed the second one to proceed, but the third
was merged with the second, even though it conflicted with the first.
So, don't allow the third to be merged with the second, since the second
stored to a different ECC granule.
 2017-08-08 15:19:05 -07:00
Andrew Waterman 7935c61c19 Don't report to the DTIM that data is cacheable 
Otherwise, it will attempt to perform AMOs where they're unsupported!
 2017-08-08 11:55:04 -07:00
Andrew Waterman 74d309c18e Make I vs. D a static property of TLB, not an input pin 
The microarchitecture doesn't really support unified TLBs, so don't fake it.
 2017-08-08 11:54:47 -07:00
Andrew Waterman e92981b0bd DRY 2017-08-08 11:46:38 -07:00
Andrew Waterman 62ccba304c Perform tag error detectoin/correction in same cycle as RAM 
The tag RAMs tend to be fast, so take up some of the slack.
This makes s2_nack faster.
 2017-08-08 10:21:30 -07:00
Andrew Waterman ea4b1bc349 Use vlsi_mem_gen for verilator flow 2017-08-07 20:36:22 -07:00
Andrew Waterman b0f32c8f09 Randomize disabled read ports in vlsi_mem_gen 2017-08-07 20:35:40 -07:00
Andrew Waterman 402907990c Revert "Remove one gate from D$ ECC check" 
This reverts commit 7d94074b05, which
works fine with optimistic behavioral RAMs but not real ones.
 2017-08-07 17:33:20 -07:00
Andrew WatermanandYunsup Lee 3d0051e799 bump tools for test fixes 2017-08-06 22:36:25 -07:00
Andrew Waterman 658e36f98b Reduce fanout on frontend io.cpu.req.valid signal 2017-08-06 17:38:51 -07:00
Andrew Waterman 7d94074b05 Remove one gate from D$ ECC check 
The D$ corrects via writeback, so which word the error was in doesn't
matter, as the entire line is corrected.
 2017-08-06 17:36:53 -07:00
Andrew Waterman 39b7e930ca Disable AMBAUnitTestConfig, as it is blocking unrelated PRs 2017-08-05 16:14:02 -07:00
Andrew Waterman 83875e3a0c Only flush D$ on FENCE.I if it won't always be probed on I$ miss 2017-08-05 14:22:40 -07:00
Andrew Waterman 991e16de92 Remove probe address mux from TLB response path 2017-08-05 12:57:38 -07:00
Andrew Waterman b9b4142bb4 Get s2_nack off the critical path 
We were using it to compute the next PC on flush vs. replay (which require
PC+4 and PC, respectively).  This fix gets rid of the adder altogether by
reusing the M-stage PC in the flush case, which by construction holds PC+4.
 2017-08-05 00:30:36 -07:00
Andrew Waterman bc298bf146 Optimize ShiftQueue for late-arriving deq.ready 2017-08-04 22:06:37 -07:00
Andrew Waterman 6112adfbb0 Get L2 TLB tag/parity check off the D$ arbitration path 2017-08-04 17:01:51 -07:00
Andrew Waterman 8d97684555 Fix L2 TLB perfctr 
It was counting conflict misses but not cold misses.
 2017-08-04 17:01:31 -07:00
Andrew Waterman df7f09b9ce Get I$ ECC check further off critical path 2017-08-04 16:59:21 -07:00
Andrew Waterman 4bfbe75d74 Avoid pipeline replays when fetch queue is full 2017-08-04 16:59:21 -07:00
Andrew Waterman a45997d03f Separate I$ parity error from miss signal 
Handle parity errors with a pipeline flush rather than a faster
frontend replay, reducing a critical path.
 2017-08-04 16:59:21 -07:00
Andrew Waterman 06a831310b Shave a gate delay off I$ backpressure path 
The deleted code was a holdover from Hwacha's vector fences.
 2017-08-04 13:12:43 -07:00
Andrew Waterman ecc2ee366c Shave a few gate delays off IBuf control logic 
It takes a while for the pipeline to compute the stall signal, so avoid
using it until the last logic levels in the clock cycle.
 2017-08-04 13:12:43 -07:00
Andrew Waterman 21ac28b57a Don't build verilog twice for emulator and emulator-debug 
Since we aren't using chisel2, the output is the same either way.
 2017-08-04 01:02:33 -07:00
Andrew Waterman f483bab4aa Fix I$ miss perfctr 
The old version was counting prefetches, too.
 2017-08-03 00:52:12 -07:00
Andrew Waterman 2537d0d54e Optionally prefetch next I$ line into L2$ on miss 2017-08-02 17:10:56 -07:00
Andrew Waterman 744cdb2f72 Make TLB report when it's safe to prefetch within a page 2017-08-02 17:09:38 -07:00
Andrew Waterman 7d2dd3769f Optimize a hazard check critical path 2017-08-02 14:27:25 -07:00
Andrew Waterman 2eb239d03f Add option to retime D$ way mux into subsequent pipeline stage 2017-08-01 23:59:20 -07:00
Andrew Waterman 9464c6db40 Mitigate(?) frontend critical path 2017-08-01 18:51:17 -07:00
Andrew Waterman 735701382f Mitigate some I$ response valid critical paths 2017-08-01 18:51:17 -07:00
Andrew Waterman 2ecea2ef60 Don't use a pipe queue on D$ TL A-channel 
This cuts an I$->D$ path.
 2017-08-01 15:17:07 -07:00
Andrew Waterman e140893a01 Use 1-entry queue on processor-side E-channel 
The cache can't sink a grant every cycle, so extra E buffering doesn't help.
 2017-07-31 18:06:54 -07:00