riscv/rocket-chip
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Remove deprecated custom-CSR support

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This commit is contained in:
Andrew Waterman 2017-09-20 13:43:25 -07:00
parent 5232a29d7d
commit 190d5c50d9
2 changed files with 0 additions and 10 deletions
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8
src/main/scala/rocket/CSR.scala
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@ -190,7 +190,6 @@ class CSRFileIO(implicit p: Parameters) extends CoreBundle
val evec = UInt(OUTPUT, vaddrBitsExtended)
val exception = Bool(INPUT)
val retire = UInt(INPUT, log2Up(1+retireWidth))
val custom_mrw_csrs = Vec(nCustomMrwCsrs, UInt(INPUT, xLen))
val cause = UInt(INPUT, xLen)
val pc = UInt(INPUT, vaddrBitsExtended)
val badaddr = UInt(INPUT, vaddrBitsExtended)
@ -438,13 +437,6 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
read_mapping += (CSRs.pmpaddr0 + i) -> pmp.addr
}
for (i <- 0 until nCustomMrwCsrs) {
val addr = 0xff0 + i
require(addr < (1 << CSR.ADDRSZ))
require(!read_mapping.contains(addr), "custom MRW CSR address " + i + " is already in use")
read_mapping += addr -> io.custom_mrw_csrs(i)
}
val decoded_addr = read_mapping map { case (k, v) => k -> (io.rw.addr === k) }
val wdata = readModifyWriteCSR(io.rw.cmd, io.rw.rdata, io.rw.wdata)

2
src/main/scala/rocket/RocketCore.scala
View File

@ -23,7 +23,6 @@ case class RocketCoreParams(
nBreakpoints: Int = 1,
nPMPs: Int = 8,
nPerfCounters: Int = 0,
nCustomMRWCSRs: Int = 0,
nL2TLBEntries: Int = 0,
mtvecInit: Option[BigInt] = Some(BigInt(0)),
mtvecWritable: Boolean = true,
@ -49,7 +48,6 @@ trait HasRocketCoreParameters extends HasCoreParameters {
val nBreakpoints = rocketParams.nBreakpoints
val nPMPs = rocketParams.nPMPs
val nPerfCounters = rocketParams.nPerfCounters
val nCustomMrwCsrs = rocketParams.nCustomMRWCSRs
val mtvecInit = rocketParams.mtvecInit
val mtvecWritable = rocketParams.mtvecWritable