Christopher Celio
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76bf1da310
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[commitlog] zero-extend SP write-back values
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2015-09-15 16:47:26 -07:00 |
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Christopher Celio
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7d14abf262
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[commitlog] Added privilege-level to output
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2015-09-15 16:47:24 -07:00 |
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Christopher Celio
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53a02a62c8
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[commitlog] Fix sp/dp bug in FPU writeback
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2015-09-15 16:46:47 -07:00 |
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Christopher Celio
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d630a03857
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[commitlog] Added FP instructions to the commitlog
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2015-09-15 15:59:13 -07:00 |
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Andrew Waterman
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78b2e947de
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Chisel3 compatibility fixes
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2015-09-11 15:43:07 -07:00 |
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Andrew Waterman
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1718333f83
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Don't use Vec as lvalue
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2015-08-05 15:29:33 -07:00 |
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Andrew Waterman
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546205b174
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Chisel3 compatibility: use >>Int instead of >>UInt
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2015-08-05 15:29:03 -07:00 |
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Andrew Waterman
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6c0e1e33ab
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Purge UInt := SInt assignments
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2015-07-31 15:42:10 -07:00 |
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Andrew Waterman
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57930e8a26
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Chisel3 compatibility potpourri
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2015-07-30 23:53:02 -07:00 |
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Andrew Waterman
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049fc8dc24
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Chisel3 compatibility: use BitPat for don't-cares
This one's hella ugly, but for the time being, idgaf.
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2015-07-28 02:48:49 -07:00 |
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Andrew Waterman
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ae73e3a997
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Only instantiate div/sqrt unit if requested
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2015-07-22 22:18:18 -07:00 |
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Andrew Waterman
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cc447c8110
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Refactor pipeline RTL (merge ctrl + dpath into rocket)
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2015-07-21 17:10:56 -07:00 |
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Andrew Waterman
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ac6e73e317
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Add Wire() wrap
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2015-07-15 20:24:18 -07:00 |
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Andrew Waterman
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be2ff6dec7
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Vec(Reg) -> Reg(Vec)
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2015-07-15 12:33:46 -07:00 |
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Andrew Waterman
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9ade0e41cc
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Integrate divide/sqrt unit
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2015-04-04 16:39:17 -07:00 |
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Yunsup Lee
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8abf62fae3
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add LICENSE
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2014-09-12 18:06:41 -07:00 |
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Adam Izraelevitz
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812353bace
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Ported FPU parameters to new Chisel Parameters
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2014-08-19 11:37:27 -07:00 |
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Andrew Waterman
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4ca152b012
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Use BundleWithConf to avoid clone method boilerplate
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2014-05-09 19:37:16 -07:00 |
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Andrew Waterman
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5996418021
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Fix exception behavior of fmin/fmax
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2014-03-18 18:36:51 -07:00 |
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Andrew Waterman
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a0389645b7
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New FP encoding; improved FP implementation
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2014-03-11 18:58:24 -07:00 |
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Andrew Waterman
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00bc1a2293
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Add fclass.{s|d} instructions
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2014-03-10 16:59:24 -07:00 |
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Andrew Waterman
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c7110c8389
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Make FPU pipeline depths configurable
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2014-02-28 13:39:59 -08:00 |
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Andrew Waterman
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95de358a96
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More of the same FPU fix
some SP ops followed by DP stores were not working because they
were encoded as subnormals, not NaNs.
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2014-01-17 14:09:30 -08:00 |
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Andrew Waterman
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cf38001e98
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Fix fmv.s.x -> fsd
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2014-01-17 03:52:35 -08:00 |
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Andrew Waterman
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924261e2b2
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Update to new privileged ISA... phew
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2013-11-25 04:35:15 -08:00 |
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Andrew Waterman
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1d2f4f8437
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New ISA encoding, AUIPC semantics
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2013-09-21 06:32:40 -07:00 |
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Andrew Waterman
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18968dfbc7
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Move store data generation into cache
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2013-09-14 16:15:07 -07:00 |
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Andrew Waterman
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d4a0db4575
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Reflect ISA changes
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2013-08-24 14:43:55 -07:00 |
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Henry Cook
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3a266cbbfa
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final Reg changes
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2013-08-15 15:28:15 -07:00 |
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Henry Cook
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b570435847
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Reg standardization
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2013-08-13 17:50:02 -07:00 |
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Henry Cook
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d9b3c7cfc8
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Moved RenEn to ChiselUtil
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2013-08-12 22:18:25 -07:00 |
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Henry Cook
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1a9e43aa11
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initial attempt at upgrade
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2013-08-12 10:39:11 -07:00 |
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Henry Cook
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9abdf4e154
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Make compatible with scala 2.10. List.sort deprecated. Refactor constants into package object.
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2013-07-23 20:27:58 -07:00 |
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Yunsup Lee
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60bd3a6413
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Revert "shuffled FPU control logic around to make functional unit retiming work better"
This reverts commit 20dd308067b143adff4913fc7ac710a393ca1d86.
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2013-01-29 19:34:55 -08:00 |
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Rimas Avizienis
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f2df6147df
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shuffled FPU control logic around to make functional unit retiming work better
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2013-01-28 17:17:09 -08:00 |
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Henry Cook
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e1225c5114
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standardize IO naming convention
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2013-01-07 13:41:36 -08:00 |
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Andrew Waterman
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4608660f6e
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torture revealed a couple bugs
FP loads/stores with certain negative offsets could cause illegal rounding
mode traps, and x's were cropping up in situations that are benign in HW.
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2012-12-04 05:57:53 -08:00 |
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Andrew Waterman
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cc067026a2
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pipeline D$ response -> FPU regfile
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2012-11-17 06:48:11 -08:00 |
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Andrew Waterman
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8dce89703a
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new D$ with better QoR and AMO pipelining
Vector unit is disabled because nack handling needs to be fixed.
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2012-11-16 02:39:33 -08:00 |
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Andrew Waterman
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4d1ca8ba3a
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remove more global consts; refactor DTLBs
D$ now contains DTLB. provide full VAddr with initial request.
VU now has its own DTLBs.
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2012-11-06 08:13:44 -08:00 |
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Andrew Waterman
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7380c9fe60
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aggressively clock gate int and fp datapaths
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2012-11-04 16:40:14 -08:00 |
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Huy Vo
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fd95159837
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INPUT/OUTPUT orderring swapped
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2012-07-12 18:16:57 -07:00 |
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Andrew Waterman
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f645fb4dd7
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add L2$
It still has performance bugs but no correctness bugs AFAIK.
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2012-07-10 05:23:29 -07:00 |
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Andrew Waterman
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5035374f36
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update to new chisel
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2012-07-08 17:59:41 -07:00 |
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Andrew Waterman
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4e5f874266
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update to new chisel/hwacha
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2012-06-08 00:13:14 -07:00 |
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Andrew Waterman
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7f6319047e
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update to new scala/chisel/Mem
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2012-06-06 02:47:22 -07:00 |
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Huy Vo
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7408c9ab69
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removing wires
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2012-05-24 10:42:39 -07:00 |
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Andrew Waterman
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65ff397122
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improved instruction decoding
it now makes use of don't-cares by performing logic minimization
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2012-05-01 20:16:36 -07:00 |
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Andrew Waterman
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5819beed64
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use parameterized FP units
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2012-05-01 01:25:43 -07:00 |
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Andrew Waterman
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7f254d9670
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refine FP bugfixes
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2012-04-01 14:52:33 -07:00 |
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