riscv/rocket-chip
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Author SHA1 Message Date
Andrew WatermanandGitHub 86a1953287 Merge pull request #1032 from freechipsproject/fpga_pipeline_fpu_master 
FPU FMA FPGA retiming assist
 2017-10-05 20:11:34 -07:00
Andrew WatermanandGitHub 5a84564203 Merge pull request #1023 from freechipsproject/csr-cleanup 
Generalize CSR file to support simpler cores
 2017-10-04 14:04:59 -07:00
Andrew WatermanandGitHub 32fda51a2c Get rid of paddrBits from SystemBus (#1029) 2017-10-04 12:11:37 -07:00
Andrew WatermanandGitHub 9137f54f59 Merge pull request #1020 from freechipsproject/fix-trace-insn 
Provide correct trace insn on interrupts when possible
 2017-09-27 18:47:24 -07:00
Andrew WatermanandGitHub 5b2f458214 Merge branch 'master' into ma-fetch 2017-09-20 12:18:03 -07:00
Andrew WatermanandGitHub f1a506476b Merge pull request #994 from freechipsproject/beu 
Add L1 bus-error unit
 2017-09-20 12:17:08 -07:00
Andrew WatermanandGitHub acea94bcef Merge pull request #1001 from freechipsproject/address-decoder 
Address decoder "improvements"
 2017-09-19 22:38:53 -07:00
Andrew WatermanandGitHub 1f606d924f Don't perform in-place correction if there was a recent store (#988) 
Since the correction updates the entire word, the WAW hazard detection
logic is not sufficient to prevent overwriting a recent store.  So,
re-read the word after all pending stores have drained.
 2017-09-08 16:26:54 -07:00
Andrew WatermanandGitHub 53dfc5e9be Remove overzealous assertion (#987) 
This assertion made sure the D$ controller was able to write the tag RAM
when a cache line was refilled.  However, it is benign if it fails to do
so: the metadata is invalid at this point, so the miss will simply happen
a second time.

This happens when resolving a tag ECC error during hit-under-miss.
 2017-09-07 18:17:56 -07:00
Andrew WatermanandGitHub 82df766f4a Merge pull request #963 from freechipsproject/interrupt-order 
Respect ISA requirements on interrupt priority order
 2017-08-18 00:10:19 -07:00
Andrew WatermanandGitHub e945f6e265 Merge pull request #955 from freechipsproject/fix-acquire-before-release 
Fix acquire before release
 2017-08-13 18:29:58 -07:00
Andrew WatermanandGitHub 41a2a03f90 Merge pull request #953 from freechipsproject/fix-dcache-ecc 
Don't trigger ECC writebacks when a release is in flight
 2017-08-12 16:47:19 -07:00
Andrew WatermanandGitHub a3358f34a0 Fix priority inversion for two back-to-back divides (#948) 
If the first one is killed for some unrelated reason (e.g. write port
hazard), the second one will still issue to the div-sqrt unit.  While
it will itself later be killed, the fact that the later instruction
acquires a resource needed by the former instruction leads to deadlock.
 2017-08-10 17:12:09 -07:00
Andrew WatermanandGitHub 0a591c5b5b Roll back use of UIntToOH1 (#946) 
These appear to be equivalent, but the old one seems to fail in Vivado and
this one seems to pass.  This is not yet conclusive.
 2017-08-09 18:39:47 -07:00
Andrew WatermanandGitHub 82e13443b2 Merge pull request #937 from freechipsproject/critical-paths 
Perform tag error detectoin/correction in same cycle as RAM
 2017-08-08 15:03:28 -07:00
Andrew WatermanandGitHub dd103ae7ec Merge pull request #938 from freechipsproject/dtim-ignore-cacheable 
Don't report to the DTIM that data is cacheable
 2017-08-08 15:00:13 -07:00
Andrew WatermanandGitHub 7fd8bb1159 Merge pull request #928 from freechipsproject/critical-paths 
Critical paths
 2017-08-06 18:50:59 -07:00
Andrew WatermanandGitHub 82ff81e40d Merge pull request #924 from freechipsproject/dont-build-debug-verilog 
Don't build verilog twice for emulator and emulator-debug
 2017-08-04 10:16:59 -07:00
Andrew WatermanandGitHub 7937db0c84 Merge pull request #919 from freechipsproject/imiss-perf-counter 
Fix I$ miss perfctr
 2017-08-04 01:04:23 -07:00
Andrew WatermanandGitHub ba4eecc0f0 Use UIntToOH1 (#921) 
Closes #920
 2017-08-03 14:55:39 -07:00
Andrew WatermanandGitHub 1be1433f04 Merge pull request #918 from freechipsproject/icache-prefetch 
Icache prefetch
 2017-08-02 21:22:20 -07:00
Andrew WatermanandGitHub d66e8f8e80 Merge pull request #914 from freechipsproject/critical-paths 
Fix some critical paths
 2017-08-02 19:05:31 -07:00
Andrew WatermanandGitHub 27d5557177 Merge pull request #891 from freechipsproject/fix-l2-tlb 
Fix L2 TLB
 2017-07-26 09:43:16 -07:00
Andrew WatermanandGitHub d43f02268b Merge pull request #889 from freechipsproject/acq-before-rel-and-jump-in-frontend 
Acquire before release; jump in frontend
 2017-07-25 16:26:47 -07:00
Andrew WatermanandGitHub a0cbc376b4 Merge pull request #849 from freechipsproject/l2-tlb 
L1 memory system improvements
 2017-07-06 13:03:06 -07:00
Andrew WatermanandGitHub e1cc0a0a0e Mask debug interrupts similarly to other interrupts (#847) 
This makes single-step exceptions higher-priority than debug interrupts.
 2017-07-06 12:03:24 -07:00
Andrew WatermanandGitHub ec9fbe26d8 Merge pull request #843 from freechipsproject/tag-ecc 
Add tag ECC to D$
 2017-07-04 16:20:11 -07:00
Andrew WatermanandGitHub 936096dd42 Merge pull request #826 from freechipsproject/tlb2 
Various memory system improvements
 2017-06-28 13:51:24 -07:00
Andrew WatermanandGitHub 72c46e6c05 Merge pull request #818 from sashimi-yzh/faster-verilator-compile 
emulator,Makefile-verilator: add --output-split-cfuncs flag
 2017-06-26 11:39:42 -07:00
Andrew WatermanandGitHub f396b4142d Merge pull request #806 from freechipsproject/mulh 
Improve integer mul/div
 2017-06-20 13:01:16 -07:00
Andrew WatermanandGitHub 4a24e9a6c6 Merge pull request #792 from freechipsproject/fix-fdiv 
Fix FPU control bug for div/sqrt
 2017-06-09 18:27:19 -07:00
Andrew WatermanandGitHub e69badb205 Merge pull request #791 from freechipsproject/tlb 
Fix I$ reset regression
 2017-06-09 15:49:25 -07:00
Andrew WatermanandGitHub 5a4daebbcc minNum -> minimumNumber (#766) 2017-06-08 11:12:52 -07:00
Andrew WatermanandGitHub 8cb250cfe6 Fix FMUL sign, again (#789) 2017-06-08 01:50:00 -07:00
Andrew WatermanandGitHub d45fc0d670 Merge pull request #785 from freechipsproject/fmul-fix 
Fix FMUL sign of zero
 2017-06-06 00:46:03 -07:00
Andrew WatermanandGitHub efce8f06b8 Merge pull request #769 from freechipsproject/new-div-sqrt 
Incorporate new div/sqrt unit
 2017-06-03 03:58:52 -07:00
Andrew WatermanandGitHub 618468a06b Make plusarg_reader default args work with VCS (#765) 
Resolves #764
 2017-05-24 21:38:56 -07:00
Andrew WatermanandHenry Cook dbc5e7c494 Add TLB miss performance counters (#762) 2017-05-23 12:52:25 -07:00
Andrew WatermanandHenry Cook b2b4c1abcd Separate tag ECC and data ECC options (#761) 2017-05-23 12:51:48 -07:00
Andrew WatermanandGitHub 3a9bbd7e58 Merge branch 'master' into vectored-stvec 2017-05-08 14:08:09 -07:00
Andrew WatermanandGitHub e21b74c232 Merge pull request #724 from ucb-bar/rvc-speculative 
Fix RVC/uncacheable instruction memory performance bug
 2017-05-03 18:48:49 -07:00
Andrew WatermanandYunsup Lee 4efcb5a139 Increase frontend decoupling (#722) 
Reduce pathological RVC stalls
 2017-05-03 07:54:46 -07:00
Andrew WatermanandYunsup Lee d6e69066a5 Fix ITIM loads (#716) 
An incorrectly-set ready signal caused bad data to be read from the RAM.
 2017-05-01 17:41:25 -07:00
Andrew WatermanandGitHub 9b688ce7e2 Merge pull request #707 from ucb-bar/itim 
ITIM
 2017-04-28 02:55:01 -07:00
Andrew WatermanandWesley W. Terpstra 8dfbf4532a Use 1 MHz as default timebase (#628) 
Defaulting to 0 prevents Linux from booting
 2017-03-28 19:59:56 -07:00
Andrew WatermanandHenry Cook 915697cb09 Fix FEQ flag generation (#479) 
FEQ is not a signaling comparison (i.e., qNaN is not an invalid input).

Also, minor code cleanup.
 2016-12-06 11:54:29 -08:00
Andrew Waterman a98127c09e Merge branch 'ss-frontend' 2015-01-04 20:26:38 -08:00
Andrew Waterman b70f7683d3 Merge branch 'master' into ss-frontend 
Conflicts:
	src/main/scala/ctrl.scala
 2015-01-04 19:59:18 -08:00
Andrew Waterman 87ad1a5703 More control cleanup 2015-01-04 19:46:01 -08:00
Andrew Waterman 2aee85cb11 Flush pipeline from MEM stage 
This means we no longer have to rely on the instruction behind a serializing
instruction being valid, simplifying the control.  But we have to be a
little more cautious when flusing the I$/ITLB/BTB.
 2015-01-04 16:40:16 -08:00
Andrew Waterman 94b75c7cb1 Continue refactoring control 2015-01-04 15:32:05 -08:00
Andrew Waterman 6181de4cc9 Much refactor, so control 2015-01-03 13:34:38 -08:00