Merge pull request #1001 from freechipsproject/address-decoder
Address decoder "improvements"
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commit
acea94bcef
@ -31,11 +31,11 @@ object AddressDecoder
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} }
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}
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val maxBits = log2Ceil(nonEmptyPorts.map(_.map(_.base).max).max)
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val (bitsToTry, bitsToTake) = (0 to maxBits).map(BigInt(1) << _).partition(b => (givenBits & b) == 0)
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val maxBits = log2Ceil(1 + nonEmptyPorts.map(_.map(_.base).max).max)
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val (bitsToTry, bitsToTake) = (0 until maxBits).map(BigInt(1) << _).partition(b => (givenBits & b) == 0)
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val partitions = Seq(nonEmptyPorts.map(_.sorted).sorted(portOrder))
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val givenPartitions = bitsToTake.foldLeft(partitions) { (p, b) => partitionPartitions(p, b) }
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val selected = recurse(givenPartitions, bitsToTry.toSeq)
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val selected = recurse(givenPartitions, bitsToTry.reverse.toSeq)
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val output = selected.reduceLeft(_ | _) | givenBits
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// Modify the AddressSets to allow the new wider match functions
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@ -70,10 +70,10 @@ object AddressDecoder
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def bitScore(partitions: Partitions): Seq[Int] = {
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val maxPortsPerPartition = partitions.map(_.size).max
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val sumPortsPerPartition = partitions.map(_.size).sum
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val maxSetsPerPartition = partitions.map(_.map(_.size).sum).max
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val sumSetsPerPartition = partitions.map(_.map(_.size).sum).sum
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Seq(maxPortsPerPartition, sumPortsPerPartition, maxSetsPerPartition, sumSetsPerPartition)
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val sumSquarePortsPerPartition = partitions.map(p => p.size * p.size).sum
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val sumSquareSetsPerPartition = partitions.map(_.map(p => p.size * p.size).sum).max
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Seq(maxPortsPerPartition, maxSetsPerPartition, sumSquarePortsPerPartition, sumSquareSetsPerPartition)
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}
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def partitionPort(port: Port, bit: BigInt): (Port, Port) = {
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@ -123,6 +123,8 @@ object AddressDecoder
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val candidates = bits.map { bit =>
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val result = partitionPartitions(partitions, bit)
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val score = bitScore(result)
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if (debug)
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println(" For bit %x, %s".format(bit, score.toString))
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(score, bit, result)
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}
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val (bestScore, bestBit, bestPartitions) = candidates.min(Ordering.by[(Seq[Int], BigInt, Partitions), Iterable[Int]](_._1.toIterable))
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