Merge pull request #1032 from freechipsproject/fpga_pipeline_fpu_master
FPU FMA FPGA retiming assist
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commit
86a1953287
@ -542,7 +542,72 @@ class FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) {
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io.out <> Pipe(in.valid, mux, latency-1)
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}
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class MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module
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{
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require(latency<=2)
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val io = new Bundle {
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val validin = Bool(INPUT)
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val op = Bits(INPUT, 2)
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val a = Bits(INPUT, expWidth + sigWidth + 1)
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val b = Bits(INPUT, expWidth + sigWidth + 1)
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val c = Bits(INPUT, expWidth + sigWidth + 1)
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val roundingMode = UInt(INPUT, 3)
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val detectTininess = UInt(INPUT, 1)
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val out = Bits(OUTPUT, expWidth + sigWidth + 1)
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val exceptionFlags = Bits(OUTPUT, 5)
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val validout = Bool(OUTPUT)
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}
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//------------------------------------------------------------------------
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//------------------------------------------------------------------------
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val mulAddRecFNToRaw_preMul =
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Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth))
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val mulAddRecFNToRaw_postMul =
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Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth))
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mulAddRecFNToRaw_preMul.io.op := io.op
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mulAddRecFNToRaw_preMul.io.a := io.a
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mulAddRecFNToRaw_preMul.io.b := io.b
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mulAddRecFNToRaw_preMul.io.c := io.c
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val mulAddResult =
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(mulAddRecFNToRaw_preMul.io.mulAddA *
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mulAddRecFNToRaw_preMul.io.mulAddB) +&
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mulAddRecFNToRaw_preMul.io.mulAddC
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val valid_stage0 = Wire(Bool())
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val roundingMode_stage0 = Wire(UInt(width=3))
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val detectTininess_stage0 = Wire(UInt(width=1))
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val postmul_regs = if(latency>0) 1 else 0
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mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits
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mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits
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mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits
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roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits
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detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits
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valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid
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//------------------------------------------------------------------------
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//------------------------------------------------------------------------
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val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0))
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val round_regs = if(latency==2) 1 else 0
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roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits
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roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits
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roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits
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roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits
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io.validout := Pipe(valid_stage0, false.B, round_regs).valid
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roundRawFNToRecFN.io.infiniteExc := Bool(false)
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io.out := roundRawFNToRecFN.io.out
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io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
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}
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class FPUFMAPipe(val latency: Int, val t: FType)(implicit p: Parameters) extends FPUModule()(p) {
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require(latency>0)
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val io = new Bundle {
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val in = Valid(new FPInput).flip
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val out = Valid(new FPResult)
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@ -560,7 +625,8 @@ class FPUFMAPipe(val latency: Int, val t: FType)(implicit p: Parameters) extends
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when (!(cmd_fma || cmd_addsub)) { in.in3 := zero }
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}
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val fma = Module(new hardfloat.MulAddRecFN(t.exp, t.sig))
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val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig))
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fma.io.validin := valid
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fma.io.op := in.fmaCmd
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fma.io.roundingMode := in.rm
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fma.io.detectTininess := hardfloat.consts.tininess_afterRounding
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@ -571,7 +637,8 @@ class FPUFMAPipe(val latency: Int, val t: FType)(implicit p: Parameters) extends
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val res = Wire(new FPResult)
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res.data := sanitizeNaN(fma.io.out, t)
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res.exc := fma.io.exceptionFlags
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io.out := Pipe(valid, res, latency-1)
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io.out := Pipe(fma.io.validout, res, (latency-3) max 0)
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}
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class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
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