Merge pull request #953 from freechipsproject/fix-dcache-ecc
Don't trigger ECC writebacks when a release is in flight
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commit
41a2a03f90
@ -100,7 +100,8 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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val s1_valid_masked = s1_valid && !io.cpu.s1_kill
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val s1_valid_not_nacked = s1_valid && !s1_nack
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val s1_req = Reg(io.cpu.req.bits)
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when (metaArb.io.out.valid && !metaArb.io.out.bits.write) {
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val s0_clk_en = metaArb.io.out.valid && !metaArb.io.out.bits.write
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when (s0_clk_en) {
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s1_req := io.cpu.req.bits
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s1_req.addr := Cat(metaArb.io.out.bits.addr >> blockOffBits, io.cpu.req.bits.addr(blockOffBits-1,0))
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when (!metaArb.io.in(7).ready) { s1_req.phys := true }
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@ -135,7 +136,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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dataArb.io.in(3).bits.wordMask := UIntToOH(io.cpu.req.bits.addr.extract(rowOffBits-1,offsetlsb))
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dataArb.io.in(3).bits.way_en := ~UInt(0, nWays)
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when (!dataArb.io.in(3).ready && s0_read) { io.cpu.req.ready := false }
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val s1_didntRead = RegEnable(s0_needsRead && !dataArb.io.in(3).ready, metaArb.io.out.valid && !metaArb.io.out.bits.write)
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val s1_did_read = RegEnable(dataArb.io.in(3).fire(), s0_clk_en)
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metaArb.io.in(7).valid := io.cpu.req.valid
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metaArb.io.in(7).bits.write := false
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metaArb.io.in(7).bits.addr := io.cpu.req.bits.addr
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@ -232,11 +233,12 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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val (s2_hit, s2_grow_param, s2_new_hit_state) = s2_hit_state.onAccess(s2_req.cmd)
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val s2_data_decoded = decodeData(s2_data)
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val s2_word_idx = s2_req.addr.extract(log2Up(rowBits/8)-1, log2Up(wordBytes))
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val s2_data_error = needsRead(s2_req) && (s2_data_decoded.map(_.error).grouped(wordBits/eccBits).map(_.reduce(_||_)).toSeq)(s2_word_idx)
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val s2_did_read = RegEnable(s1_did_read, s1_valid_not_nacked)
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val s2_data_error = s2_did_read && (s2_data_decoded.map(_.error).grouped(wordBits/eccBits).map(_.reduce(_||_)).toSeq)(s2_word_idx)
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val s2_data_corrected = (s2_data_decoded.map(_.corrected): Seq[UInt]).asUInt
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val s2_data_uncorrected = (s2_data_decoded.map(_.uncorrected): Seq[UInt]).asUInt
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val s2_valid_hit_pre_data_ecc = s2_valid_masked && s2_readwrite && !s2_meta_error && s2_hit
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val s2_valid_data_error = s2_valid_hit_pre_data_ecc && s2_data_error
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val s2_valid_data_error = s2_valid_hit_pre_data_ecc && s2_data_error && !release_ack_wait
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val s2_valid_hit = s2_valid_hit_pre_data_ecc && !s2_data_error && (!s2_waw_hazard || s2_store_merge)
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val s2_valid_miss = s2_valid_masked && s2_readwrite && !s2_meta_error && !s2_hit && !release_ack_wait
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val s2_valid_cached_miss = s2_valid_miss && !s2_uncached && !uncachedInFlight.asUInt.orR
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@ -348,7 +350,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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(pstore1_valid && s1Depends(pstore1_addr, pstore1_mask)) ||
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(pstore2_valid && s1Depends(pstore2_addr, pstore2_storegen_mask))
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val s1_raw_hazard = s1_read && s1_hazard
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s1_waw_hazard := Bool(eccBytes > 1) && s1_write && (s1_hazard || s1_didntRead)
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s1_waw_hazard := Bool(eccBytes > 1) && s1_write && (s1_hazard || needsRead(s1_req) && !s1_did_read)
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when (s1_valid && s1_raw_hazard) { s1_nack := true }
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// Prepare a TileLink request message that initiates a transaction
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@ -409,7 +411,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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val grantInProgress = Reg(init=Bool(false))
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val blockProbeAfterGrantCount = Reg(init=UInt(0))
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when (blockProbeAfterGrantCount > 0) { blockProbeAfterGrantCount := blockProbeAfterGrantCount - 1 }
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val canAcceptCachedGrant = if (cacheParams.acquireBeforeRelease) release_state === s_ready else true.B
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val canAcceptCachedGrant = if (cacheParams.acquireBeforeRelease) !release_state.isOneOf(s_voluntary_writeback, s_voluntary_write_meta) else true.B
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tl_out.d.ready := Mux(grantIsCached, (!d_first || tl_out.e.ready) && canAcceptCachedGrant, true.B)
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when (tl_out.d.fire()) {
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when (grantIsCached) {
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