riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Merge pull request #724 from ucb-bar/rvc-speculative

Browse Source 
Fix RVC/uncacheable instruction memory performance bug
This commit is contained in:
Andrew Waterman 2017-05-03 18:48:49 -07:00 committed by GitHub
commit e21b74c232
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/rocket/Frontend.scala
View File

@ -158,7 +158,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
icache.io.s1_paddr := tlb.io.resp.paddr
icache.io.s2_vaddr := s2_pc
icache.io.s1_kill := io.cpu.req.valid || tlb.io.resp.miss || s2_replay
icache.io.s2_kill := s2_speculative && !s2_cacheable || s2_xcpt
icache.io.s2_kill := RegNext(RegNext(s0_valid)) && s2_speculative && !s2_cacheable || s2_xcpt
fq.io.enq.valid := s2_valid && (icache.io.resp.valid || icache.io.s2_kill)
fq.io.enq.bits.pc := s2_pc