Andrew Waterman
1e1926ce63
flip direction of ioPipe to match ioDecoupled
2012-03-02 16:18:32 -08:00
Henry Cook
7406908d4a
BroadcastHub can be elaborated by C and vlsi backends
2012-03-02 12:19:27 -08:00
Yunsup Lee
54baa0713c
hack fence.g.cv to support waiting the control processor
2012-03-02 02:10:26 -08:00
Yunsup Lee
1054cec087
add vec countq interface
2012-03-02 00:43:32 -08:00
Yunsup Lee
8678b3d70c
clean up ioDecoupled/ioPipe interface
2012-03-01 20:48:46 -08:00
Andrew Waterman
6d03d75835
improve D$ internal interfaces
2012-03-01 20:20:15 -08:00
Andrew Waterman
28cacd953f
D$ cleanup - merge ReplayUnit and MSHRFile
2012-03-01 19:30:56 -08:00
Andrew Waterman
52101373e0
clean up D$ store data unit
2012-03-01 19:20:00 -08:00
Henry Cook
da39810bb2
Fixed elaboration errors in LockingArbiter and BoradcastHub. Fixed ioDecoupled direction error in XactTracker
2012-03-01 18:24:22 -08:00
Henry Cook
9d7707a0a2
Made xact_rep an ioValid, removed has_data member
2012-03-01 18:24:21 -08:00
Yunsup Lee
c7b01230f4
fix mul/div when waddr=0, can't believe torture didn't find this one
2012-03-01 10:15:27 -08:00
Henry Cook
c6162ac743
Unified hub ios. Fixed some hub elaboration errors.
2012-03-01 01:20:57 -08:00
Yunsup Lee
a8ef5e9e27
change NMSHR when HAVE_VEC is true
2012-03-01 01:07:47 -08:00
Yunsup Lee
6847160343
refactor arbiter priorities
2012-03-01 00:22:34 -08:00
Yunsup Lee
f641b44fb8
changes after the module uniquify bug fix
2012-02-29 22:00:59 -08:00
Henry Cook
813ffcbf3e
Finished broadcast hub with split mem req types. Untested.
2012-02-29 17:58:15 -08:00
Yunsup Lee
4939b72ba5
Merge branch 'master' of github.com:ucb-bar/riscv-rocket
2012-02-29 17:12:02 -08:00
Yunsup Lee
20d0088f66
temporary fix to match bit widths for Mem
2012-02-29 17:09:31 -08:00
Henry Cook
008ad1f45b
Added 'locking' arbiter that won't rearbitrate until the lock signal on the current winning input is low
2012-02-29 17:05:06 -08:00
Henry Cook
c723ef4c50
ioDecoupled now allows inner bundle to be used in covariant positions, i.e. it accepts subtypes
2012-02-29 16:46:16 -08:00
Andrew Waterman
c38065d0e8
clean up priority encoders
2012-02-29 16:13:14 -08:00
Andrew Waterman
b9ec69f8f5
add new Queue singleton
2012-02-29 14:21:42 -08:00
Andrew Waterman
012da6002e
replace tile memory interface with ioTileLink
...
work in progress towards coherent HTIF. for now, requests
are incoherently passed through a null coherence hub.
2012-02-29 03:10:47 -08:00
Henry Cook
082b38d315
Broadcast hub nears completion. Still does not handle generation/arbitration for decoupled mem reqs.
2012-02-29 02:59:27 -08:00
Henry Cook
8ff6e21e3a
Fixed race between read resps/reps and write req/reps in null hub
2012-02-29 00:44:03 -08:00
Andrew Waterman
c99f6bbeb7
separate memory request command and data
...
also, merge some VLSI/C++ test harness functionality
2012-02-28 19:06:23 -08:00
Henry Cook
040aa9fe02
Added temporary ioMemHub and made coherence hub implementations depend on it rather than ioMem
2012-02-28 17:33:32 -08:00
Daiwei Li
3f998b1353
send vcfg and setvl to vu prefetch queues
2012-02-28 14:54:48 -08:00
Henry Cook
5cc10337b4
Null coherence hub. Begin work on internal tracker logic
2012-02-27 19:10:15 -08:00
Andrew Waterman
2b1c07c723
replace ioDCache with ioMem
2012-02-27 18:36:09 -08:00
Andrew Waterman
1d41a41afa
remove extraneous constants
2012-02-27 17:49:48 -08:00
Yunsup Lee
3d96a2d4f0
add fpu.dec.wen := false when HAVE_FPU is turned off
2012-02-27 14:00:58 -08:00
Henry Cook
f0588a0052
Added probe_req ready sigs, GenArray to Vec
2012-02-27 11:26:18 -08:00
Henry Cook
7a8f53a117
probe req transactors in coherence hub
2012-02-27 09:24:33 -08:00
Henry Cook
2275239f33
xact init transactors in coherence hub
2012-02-27 09:24:32 -08:00
Yunsup Lee
bfd0ae125e
upgrade to new rocket/vu memory interface, fix amo nack bug in hellacache
2012-02-26 23:46:51 -08:00
Andrew Waterman
6e706c7c74
fix yet another AMO-related replay bug
2012-02-26 20:20:45 -08:00
Andrew Waterman
e12b9eae93
remove ext_mem interface
...
hindsight is 20/20
2012-02-26 18:53:39 -08:00
Andrew Waterman
2d04664a98
simplify cpu-cache interface
2012-02-26 18:26:29 -08:00
Andrew Waterman
ad713a5d83
fix icache ram depth; new chisel
2012-02-26 17:51:46 -08:00
Yunsup Lee
f3bb02b2ea
refactored dmem arbiter
2012-02-26 17:38:08 -08:00
Huy Vo
93f41d3359
Merge branch 'master' of github.com:ucb-bar/riscv-rocket
2012-02-26 17:24:23 -08:00
Huy Vo
5b0f7ccf68
updating rocket code to lastest version of chisel, passes assembly tests in C++ and Verilog as long as you dont use the vector unit
2012-02-26 17:24:08 -08:00
Yunsup Lee
766a039ffe
small changes to the dtlb arbiter
2012-02-26 16:19:50 -08:00
Daiwei Li
69260756bd
change ppn and vpn in dtlb from ufix to bits
2012-02-26 02:54:31 -08:00
Yunsup Lee
49efe4b744
now vu steals cycles from the fpu's fma alu
2012-02-26 01:55:07 -08:00
Daiwei Li
47dbc2a417
head should be working again
2012-02-26 00:30:50 -08:00
Daiwei Li
569698b824
dtlb now arbitrates between cpu, vec, and vec pf
2012-02-25 22:05:30 -08:00
Yunsup Lee
94ba32bbd3
change package name and sbt project name to rocket
2012-02-25 17:09:26 -08:00
Yunsup Lee
946e0c6e4e
add vector exception infrastructure
2012-02-25 16:37:56 -08:00
Yunsup Lee
3839e3a318
massive refactoring of vector constants
2012-02-25 15:55:36 -08:00
Henry Cook
3980120279
More stylish bundle param names, some hub progress
2012-02-25 15:27:53 -08:00
Henry Cook
db6d480778
Better foldR
2012-02-25 15:27:09 -08:00
Henry Cook
df97de0fd3
Better abstraction of data bundles
2012-02-25 12:57:01 -08:00
Henry Cook
4fa31b300b
Added popcount util
2012-02-25 12:57:01 -08:00
Yunsup Lee
a1600d95db
fix bug related to waddr and wdata in wb stage
...
for the instructions which don't use waddr/wdata for writeback, the contents were getting overwritten by the ll ops
it manifested itself after cp imul were sharing the alu with the vu
2012-02-25 12:21:10 -08:00
Yunsup Lee
137fd62007
refactor cpfences
2012-02-25 12:20:36 -08:00
Andrew Waterman
4121fb178c
clean up mul/div interface; use VU mul if HAVE_VEC
2012-02-24 19:22:35 -08:00
Andrew Waterman
b3a3289d34
fix (?) external memory request nack interface
2012-02-24 01:42:33 -08:00
Daiwei Li
477f3cde02
added prefetch queues for vu
2012-02-24 00:44:13 -08:00
Yunsup Lee
63939efd0c
fix ctrl vec iface hookup - final
2012-02-23 23:03:44 -08:00
Yunsup Lee
bf1e643913
fix ctrl vec iface hookup
2012-02-23 22:55:25 -08:00
Andrew Waterman
7b3cce79e3
allocate a primary miss on a prefetch
2012-02-23 22:40:24 -08:00
Yunsup Lee
2ea309cf80
bug fixes to ctrl_vec
2012-02-23 22:35:05 -08:00
Yunsup Lee
91a0bb6f61
add vector prefetch queues
2012-02-23 22:30:38 -08:00
Andrew Waterman
012028efaa
fix fpga build
2012-02-23 22:19:38 -08:00
Henry Cook
52da831aa3
finished xact_finish and xact_abort transactors in coherence hub
2012-02-23 18:12:50 -08:00
Henry Cook
1c1ce7d60b
finished xact_rep transactor in coherence hub
2012-02-23 17:50:02 -08:00
Andrew Waterman
5332bab6f1
expose FMA ports outside of FPU (for the VU)
2012-02-23 17:39:34 -08:00
Andrew Waterman
6ceaa0e80a
correct and simplify replay_next logic
2012-02-23 16:52:52 -08:00
Andrew Waterman
f939088be1
move datapath control signals into control unit
...
because that's where control signals go
2012-02-23 16:52:52 -08:00
Yunsup Lee
e53792a1eb
fix bug in rocket's vector datapath related to wakeup
2012-02-23 10:14:14 -08:00
Andrew Waterman
7c929afe2b
HTIF now controls CPU reset
2012-02-22 19:30:03 -08:00
Andrew Waterman
3eebf40310
nack CPU requests during any replay
2012-02-22 18:37:13 -08:00
Henry Cook
62837537f4
Improved TileIO organization, beginnings of hub implementation
2012-02-22 18:24:52 -08:00
Henry Cook
24a32c2811
Refining tilelink interface
2012-02-22 12:15:47 -08:00
Henry Cook
18bd0c232b
Added coherence message type enums
2012-02-22 12:15:47 -08:00
Daiwei Li
22f8dd0994
Hook up resp_type to vector unit
2012-02-21 18:20:32 -08:00
Andrew Waterman
cfd79c731b
add resp_type to ext_mem interface
2012-02-21 17:42:00 -08:00
Andrew Waterman
9a80adef50
only instantiate VI$ if HAVE_VEC
2012-02-21 15:53:19 -08:00
Andrew Waterman
c8f768c8b3
fix AMO replay bug
...
like the recent AMO bug fix, but affects stores too. oops.
2012-02-21 14:39:54 -08:00
Andrew Waterman
d5608b2728
fix AMO replay bug
...
didn't check for structural hazard on AMO unit
if a replay was initiated one cycle before before
a hit-under-miss AMO was issued
2012-02-21 01:02:16 -08:00
Andrew Waterman
6135615104
unify cache backend interfaces; generify arbiter
2012-02-20 00:51:48 -08:00
Andrew Waterman
7034c9be65
new htif protocol and implementation
...
You must update your fesvr and isasim!
2012-02-19 23:15:45 -08:00
Andrew Waterman
9af86633d7
invalidate I$ prefetcher when invalidating I$
2012-02-17 17:56:01 -08:00
Henry Cook
e555fd3fc4
Abstract class for coherence policies
2012-02-16 12:59:38 -08:00
Henry Cook
d46e59a16d
Abstract base nbcache class
2012-02-16 12:34:51 -08:00
Henry Cook
124efe5281
Replace nbcache manipulation of meta state bits with abstracted functions
2012-02-16 10:43:40 -08:00
Henry Cook
619929eba1
Added coherence tile function defs, with traits and constants
2012-02-16 00:16:45 -08:00
Andrew Waterman
1b5e39e7fc
fix bug in BTB
...
a BTB update followed by a taken branch could cause incorrect control flow.
2012-02-15 21:36:08 -08:00
Andrew Waterman
fc5ba769da
disable vector unit by default
2012-02-15 18:58:41 -08:00
Andrew Waterman
8b3b3abd3d
fix external memory request nack logic
2012-02-15 18:57:40 -08:00
Andrew Waterman
fe2c1d1321
add vec->ctrl fences
2012-02-15 18:31:19 -08:00
Yunsup Lee
82cd3625c2
add in vackq interface
2012-02-15 17:53:24 -08:00
Andrew Waterman
c13524ad3a
fix vcmdq full replay logic
2012-02-15 17:49:12 -08:00
Yunsup Lee
258d050e1b
add stall logic for vector command queues
2012-02-15 14:48:41 -08:00
Yunsup Lee
32bdf5098a
refactor vector control logic & datapath in the rocket core
2012-02-15 13:30:22 -08:00
Yunsup Lee
7c11c1406c
vector-vector add working!
2012-02-15 02:28:07 -08:00
Yunsup Lee
6bdf9dc513
hwacha integration: now it compiles correctly!
2012-02-14 23:34:57 -08:00
Yunsup Lee
a51c7cc927
new build system with updated chisel, hwacha
2012-02-14 19:43:59 -08:00