riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
5,393 Commits 1 Branch 0 Tags 13 MiB
6a0150aad7
Commit Graph

99 Commits

Author SHA1 Message Date
Wesley W. Terpstra
6f3a4cd733 build: pass annotations to firrtl 2017-10-10 23:42:55 -07:00
Andrew Waterman
ea4b1bc349 Use vlsi_mem_gen for verilator flow 2017-08-07 20:36:22 -07:00
Andrew Waterman
21ac28b57a Don't build verilog twice for emulator and emulator-debug 
Since we aren't using chisel2, the output is the same either way.
 2017-08-04 01:02:33 -07:00
Ben Keller
85ac8d588c Excise the last instance of run-bmarks-test (#836) 2017-06-30 11:50:40 -07:00
Zihao Yu
fc85a3ce02 emulator,Makefile-verilator: add --output-split-cfuncs flag 
* Originally verilator will generate a large cpp file containing a large
  function, which costs about 13 min to compile. By using --output-split-cfuncs,
  this large function will be splitted into several functions in servral
  files. This will greatly improve the compile time with 'make -j'. By '-j32',
  the compile time can be reduced to about 1 min.
 2017-06-26 14:29:29 +08:00
Wesley W. Terpstra
9eae1fa377 verilator: bump to version 3.904 2017-06-01 10:59:39 -07:00
Schuyler Eldridge
c61714a465 Pass MODEL variable to emulator.cc 
This enables hot-swapping of the top-level test harness by specifying
`MODEL=MyTestHarness` when building the emulator.
 2017-03-30 02:08:01 -07:00
Wesley W. Terpstra
e51609aec0 build: support waveform debug using opensource tools 
VCS is not free. Neither is the vcd format.
Fortunately, verilator and gtkwave ARE free ... and faster too.

This patch adds targets:
	run-regression-tests-fst
	run-asm-tests-fst
... which create opensource-compatible fst waveforms for gtkwave.
 2017-02-17 03:38:17 +01:00
Wesley W. Terpstra
93b2fa197e Artefact output (#545) 
* build: stop using empty .prm file

* generator: general-purpose mechanism for creating elaboration artefacts
 2017-02-02 19:24:55 -08:00
Henry Cook
c981f8b4f3 More travis job re-balancing (#481) 
* [travis] Depend on pre-built docker images rather than travis cache
 2016-12-11 22:02:46 -08:00
Henry Cook
9fb7934a37 WIP PR to figure out why travis is failing (#471) 
Make travis use a docker image with pre-built toolchain and verilator
 2016-12-04 13:10:13 -08:00
Wesley W. Terpstra
3d1a7bd6d3 travis: build verilator and toolchain as part of install 2016-11-21 21:13:26 -08:00
Andrew Waterman
f3c726033a Make all Chisel invocations depend on FIRRTL_JAR 2016-10-28 11:56:05 -07:00
Andrew Waterman
4f6eb38eeb Enable Verilator parallel builds 2016-10-04 22:29:39 -07:00
Howard Mao
10df142ac7 fix emulator path to use PROJECT instead of MODEL 2016-09-26 17:28:21 -07:00
Henry Cook
411ee378de Provide a GeneratorApp object per user package. Extract RocketTestSuite from coreplex into rocketchip and provide GeneratorApp defaults for other target packages. 2016-09-22 15:59:29 -07:00
Henry Cook
ddcf1b4099 Use PROJECT rather than MODEL in name of binary and generated src files. 2016-09-19 13:23:17 -07:00
Henry Cook
9e2b0aad65 Revert "allow MODEL to be something other than TestHarness" 
This reverts commit bf253aaa97.
 2016-09-15 11:53:05 -07:00
Howard Mao
bf253aaa97 allow MODEL to be something other than TestHarness 2016-09-14 20:51:56 -07:00
Colin Schmidt
cf3c6fa277 add STOP_COND to emulator & match vsim PRINTF_COND 2016-09-09 11:07:17 -07:00
Colin Schmidt
ba4b3e14cc remove remaining dramsim2 files 2016-09-04 17:25:24 -07:00
Howard Mao
08089f695d allow configuration to be in separate project from test harness 2016-09-01 10:28:07 -07:00
Henry Cook
93c801f598 Streamline the Generator App and associated utilities. Remove deprecated call to chiselMain and useless Chisel2 args. Update arguments to sbt run. (#227) 2016-08-25 17:26:28 -07:00
Ben Keller
4f388add67 More accurate conditional include of generated .d make fragment (#222) 2016-08-25 14:42:04 -07:00
Andrew Waterman
ed827678ac Write test harness in Chisel 
This is an unavoidably invasive commit, because it affects the unit tests
(which formerly exited using stop()), the test harness Verilog generator
(since it is no longer necessary), and the DRAM model (since it is no
longer connected).  However, this should substantially reduce the effort
of building test harnesses in the future, since manual or semi-automatic
Verilog writing should no longer be necessary.  Furthermore, there is now
very little duplication of effort between the Verilator and VCS test
harnesses.

This commit removes support for DRAMsim, which is a bit of an unfortunate
consequence.  The main blocker is the lack of Verilog parameterization for
BlackBox.  It would be straightforward to revive DRAMsim once support for
that feature is added to Chisel and FIRRTL.  But that might not even be
necessary, as we move towards synthesizable DRAM models and FAME-1
transformations.
 2016-08-15 23:27:27 -07:00
Howard Mao
dd1fed41b6 generate BootROM contents from assembly code 2016-08-05 16:39:21 -07:00
Andrew Waterman
9751ea0f35 Fix Verilator VCD (#157) 2016-07-09 02:37:39 -07:00
Andrew Waterman
32ee5432dd Fix testing of DefaultSmallConfig; bump rocket et al 2016-07-07 21:23:49 -07:00
Andrew Waterman
f1cbb2ff77 Turn up optimization for Verilator compilation 2016-06-28 14:12:46 -07:00
Andrew Waterman
568bfa6c50 Purge legacy HTIF things 
The SCR file is gone, too, because it was tightly coupled.  The
general concept could be revived as a module that somehow connects
to the debug module.
 2016-06-23 13:23:57 -07:00
Howard Mao
daa0f3038f invoke firrtl jar directly in order to control heap memory usage 2016-06-20 13:02:31 -07:00
Andrew Waterman
4a8e6c773a Fix +verbose flag for verilator 2016-06-17 21:09:08 -07:00
Palmer Dabbelt
25ade44fe3 Don't build the Verilator man pages (#141) 
These failed for Andrew earlier.  While it might be paranioa, there's
really no reason to build the man pages so we might as well not bother.
 2016-06-16 10:13:21 -07:00
Palmer Dabbelt
1525b4717e Install Verilator when building the emulator 
We need a fairly new version of Verilator, so I just added a rule to
download and install it on all systems.
 2016-06-14 21:21:43 -07:00
Palmer Dabbelt
571b5b2093 Prevent sbt from running multiple times in emulator 
If you have multi-target rules that don't have %s in them, make
interprets that as "run this recipe multiple times, once to produce each
target".  If you have %s in the rules, then make interprets it as "run
this recipe once to produce all targets".  We want the second one.
 2016-06-14 11:59:20 -07:00
Yunsup Lee
3ce8dbb6e5 fix make error mixing implicit and normal rules 2016-06-14 11:59:20 -07:00
Donggyu Kim
99b257316e replace emulator with verilator for chisel3 2016-06-08 02:43:54 -07:00
Andrew Waterman
e82c080c3c Add blocking D$ 2016-05-25 11:09:50 -07:00
Howard Mao
f52fc655a5 remove zscale 2016-05-19 09:43:15 -07:00
Andrew Waterman
46bbbba5e6 New address map 2016-04-30 20:59:36 -07:00
Howard Mao
85cc632d5d fix emulator debug build 2016-02-19 23:13:57 -08:00
Palmer Dabbelt
db9de94588 Generate and use SCR address header files 
This uses the new SCRFile changes to generate a header file containing a list
of all the SCRs in a core to remove the magic constant "63" (the HTIF clock
divider control register) and replace it with a generated number (which is
still 63).
 2016-02-17 15:23:18 -08:00
Palmer Dabbelt
07f0e6be94 Don't re-generate the .d files on "make clean" 2015-11-12 00:41:55 -08:00
Howard Mao
bbf14ddc01 use definitions in consts header whenever possible 2015-11-05 10:48:32 -08:00
Howard Mao
ba5a6af05c correctly stripe data across memory channels in simulation 2015-11-05 10:48:32 -08:00
Howard Mao
dcef020ca0 get multichannel simulation working in emulator 2015-11-05 10:48:32 -08:00
Andrew Waterman
996670a4a6 Point to correct Chisel commit 2015-10-01 10:31:29 -07:00
Christopher Celio
c2344ee2bc Added generated-src-debug to make clean target 2015-09-11 19:07:33 -07:00
Christopher Celio
8f71c4da2d Reintroduced multiple emulator backend directories 
Fixes a "make -j" concurrency bug due to deleting files that another
  parallel rule depends on.
 2015-09-10 17:14:23 -07:00
Henry Cook
ee531dc97e Add missing changes to emulator/Makefile 2015-07-29 18:15:21 -07:00