replace emulator with verilator for chisel3
This commit is contained in:
Donggyu Kim
@ -13,46 +13,16 @@ include $(base_dir)/Makefrag
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CXXSRCS := emulator mm mm_dramsim2
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CXXFLAGS := $(CXXFLAGS) -std=c++11 -I$(RISCV)/include -I$(base_dir)/csrc -I$(base_dir)/dramsim2
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LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L. -ldramsim -lfesvr -lpthread
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OBJS := $(addsuffix .o,$(CXXSRCS) $(MODEL).$(CONFIG))
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DEBUG_OBJS := $(addsuffix .debug.o,$(CXXSRCS) $(MODEL).$(CONFIG))
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model_header = $(generated_dir)/$(MODEL).$(CONFIG).h
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model_header_debug = $(generated_dir_debug)/$(MODEL).$(CONFIG).h
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$(MODEL).$(CONFIG).o: %.o: $(generated_dir)/%.h
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$(MAKE) -j $(patsubst %.cpp,%.o,$(shell ls $(generated_dir)/$(MODEL).$(CONFIG)-*.cpp))
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$(LD) -r $(patsubst %.cpp,%.o,$(shell ls $(generated_dir)/$(MODEL).$(CONFIG)-*.cpp)) -o $@
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$(MODEL).$(CONFIG).debug.o: %.debug.o: $(generated_dir_debug)/%.h
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$(MAKE) -j $(patsubst %.cpp,%.o,$(shell ls $(generated_dir_debug)/$(MODEL).$(CONFIG)-*.cpp))
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$(LD) -r $(patsubst %.cpp,%.o,$(shell ls $(generated_dir_debug)/$(MODEL).$(CONFIG)-*.cpp)) -o $@
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$(generated_dir)/%.o: $(generated_dir)/%.cpp $(generated_dir)/%.h
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$(CXX) $(CXXFLAGS) -I$(generated_dir) -c -o $@ $<
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$(generated_dir_debug)/%.o: $(generated_dir_debug)/%.cpp $(generated_dir_debug)/%.h
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$(CXX) $(CXXFLAGS) -I$(generated_dir_debug) -c -o $@ $<
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$(addsuffix .o,$(CXXSRCS)): %.o: $(base_dir)/csrc/%.cc $(base_dir)/csrc/*.h $(model_header) $(consts_header)
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$(CXX) $(CXXFLAGS) -include $(scr_header) -include $(model_header) -include $(consts_header) -I$(generated_dir) -c -o $@ $<
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$(addsuffix .debug.o,$(CXXSRCS)): %.debug.o: $(base_dir)/csrc/%.cc $(base_dir)/csrc/*.h $(model_header_debug) $(consts_header_debug)
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$(CXX) $(CXXFLAGS) -include $(scr_header_debug) -include $(model_header_debug) -include $(consts_header_debug) -I$(generated_dir_debug) -c -o $@ $<
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$(generated_dir)/$(MODEL).$(CONFIG).d $(model_header) $(params_file): $(chisel_srcs)
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cd $(base_dir) && $(SBT) "project $(PROJECT)" "run $(CHISEL_ARGS) --noIoDebug"
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$(model_header_debug) $(params_file_debug): $(chisel_srcs)
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cd $(base_dir) && $(SBT) "project $(PROJECT)" "run $(CHISEL_ARGS)-debug --debug --vcd --ioDebug"
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LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L$(abspath $(sim_dir)) -ldramsim -lfesvr -lpthread
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emu = emulator-$(MODEL)-$(CONFIG)
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$(emu): $(model_header) $(OBJS) libdramsim.a
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$(CXX) $(CXXFLAGS) -o $@ $(OBJS) $(LDFLAGS)
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emu_debug = emulator-$(MODEL)-$(CONFIG)-debug
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$(emu_debug): $(generated_dir)/$(MODEL).$(CONFIG).d $(model_header_debug) $(DEBUG_OBJS) libdramsim.a
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$(CXX) $(CXXFLAGS) -o $@ $(DEBUG_OBJS) $(LDFLAGS)
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ifeq ($(CHISEL_VERSION),2)
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include $(sim_dir)/Makefrag-emulator
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else
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include $(sim_dir)/Makefrag-verilator
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endif
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all: $(emu)
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debug: $(emu_debug)
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@ -73,16 +43,16 @@ ifneq ($(MAKECMDGOALS),clean)
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-include $(generated_dir)/$(MODEL).$(CONFIG).d
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endif
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$(output_dir)/%.run: $(output_dir)/% emulator-$(MODEL)-$(CONFIG)
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$(output_dir)/%.run: $(output_dir)/% $(emu)
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./$(emu) +dramsim +max-cycles=$(timeout_cycles) $< 2> /dev/null 2> $@ && [ $$PIPESTATUS -eq 0 ]
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$(output_dir)/%.out: $(output_dir)/% emulator-$(MODEL)-$(CONFIG)
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$(output_dir)/%.out: $(output_dir)/% $(emu)
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./$(emu) +dramsim +max-cycles=$(timeout_cycles) +verbose $< $(disasm) $@ && [ $$PIPESTATUS -eq 0 ]
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$(output_dir)/%.vcd: $(output_dir)/% emulator-$(MODEL)-$(CONFIG)-debug
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$(output_dir)/%.vcd: $(output_dir)/% $(emu_debug)
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./$(emu_debug) +dramsim +max-cycles=$(timeout_cycles) +verbose -v$@ $< $(disasm) $(patsubst %.vcd,%.out,$@) && [ $$PIPESTATUS -eq 0 ]
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$(output_dir)/%.vpd: $(output_dir)/% emulator-$(MODEL)-$(CONFIG)-debug
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$(output_dir)/%.vpd: $(output_dir)/% $(emu_debug)
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rm -rf $@.vcd && mkfifo $@.vcd
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vcd2vpd $@.vcd $@ > /dev/null &
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./$(emu_debug) +dramsim +max-cycles=$(timeout_cycles) +verbose -v$@.vcd $< $(disasm) $(patsubst %.vpd,%.out,$@) && [ $$PIPESTATUS -eq 0 ]
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40
emulator/Makefrag-emulator
Normal file
40
emulator/Makefrag-emulator
Normal file
@ -0,0 +1,40 @@
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#--------------------------------------------------------------------
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# Chisel Emulator Generation
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#--------------------------------------------------------------------
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OBJS := $(addsuffix .o,$(CXXSRCS) $(MODEL).$(CONFIG))
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DEBUG_OBJS := $(addsuffix .debug.o,$(CXXSRCS) $(MODEL).$(CONFIG))
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model_header = $(generated_dir)/$(MODEL).$(CONFIG).h
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model_header_debug = $(generated_dir_debug)/$(MODEL).$(CONFIG).h
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$(MODEL).$(CONFIG).o: %.o: $(generated_dir)/%.h
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$(MAKE) -j $(patsubst %.cpp,%.o,$(shell ls $(generated_dir)/$(MODEL).$(CONFIG)-*.cpp))
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$(LD) -r $(patsubst %.cpp,%.o,$(shell ls $(generated_dir)/$(MODEL).$(CONFIG)-*.cpp)) -o $@
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$(MODEL).$(CONFIG).debug.o: %.debug.o: $(generated_dir_debug)/%.h
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$(MAKE) -j $(patsubst %.cpp,%.o,$(shell ls $(generated_dir_debug)/$(MODEL).$(CONFIG)-*.cpp))
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$(LD) -r $(patsubst %.cpp,%.o,$(shell ls $(generated_dir_debug)/$(MODEL).$(CONFIG)-*.cpp)) -o $@
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$(generated_dir)/%.o: $(generated_dir)/%.cpp $(generated_dir)/%.h
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$(CXX) $(CXXFLAGS) -I$(generated_dir) -c -o $@ $<
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$(generated_dir_debug)/%.o: $(generated_dir_debug)/%.cpp $(generated_dir_debug)/%.h
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$(CXX) $(CXXFLAGS) -I$(generated_dir_debug) -c -o $@ $<
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$(addsuffix .o,$(CXXSRCS)): %.o: $(base_dir)/csrc/%.cc $(base_dir)/csrc/*.h $(model_header) $(consts_header)
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$(CXX) $(CXXFLAGS) -include $(scr_header) -include $(model_header) -include $(consts_header) -I$(generated_dir) -c -o $@ $<
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$(addsuffix .debug.o,$(CXXSRCS)): %.debug.o: $(base_dir)/csrc/%.cc $(base_dir)/csrc/*.h $(model_header_debug) $(consts_header_debug)
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$(CXX) $(CXXFLAGS) -include $(scr_header_debug) -include $(model_header_debug) -include $(consts_header_debug) -I$(generated_dir_debug) -c -o $@ $<
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$(generated_dir)/$(MODEL).$(CONFIG).d $(model_header) $(params_file): $(chisel_srcs)
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cd $(base_dir) && $(SBT) "project $(PROJECT)" "run $(CHISEL_ARGS) --noIoDebug"
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$(model_header_debug) $(params_file_debug): $(chisel_srcs)
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cd $(base_dir) && $(SBT) "project $(PROJECT)" "run $(CHISEL_ARGS)-debug --debug --vcd --ioDebug"
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$(emu): $(model_header) $(OBJS) libdramsim.a
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$(CXX) $(CXXFLAGS) -o $@ $(OBJS) $(LDFLAGS)
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$(emu_debug): $(generated_dir)/$(MODEL).$(CONFIG).d $(model_header_debug) $(DEBUG_OBJS) libdramsim.a
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$(CXX) $(CXXFLAGS) -o $@ $(DEBUG_OBJS) $(LDFLAGS)
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57
emulator/Makefrag-verilator
Normal file
57
emulator/Makefrag-verilator
Normal file
@ -0,0 +1,57 @@
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#--------------------------------------------------------------------
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# Verilator Generation
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#--------------------------------------------------------------------
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firrtl = $(generated_dir)/$(MODEL).$(CONFIG).fir
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firrtl_debug = $(generated_dir_debug)/$(MODEL).$(CONFIG).fir
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verilog = $(generated_dir)/$(MODEL).$(CONFIG).v
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verilog_debug = $(generated_dir_debug)/$(MODEL).$(CONFIG).v
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FIRRTL ?= $(base_dir)/firrtl/utils/bin/firrtl
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$(FIRRTL):
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$(MAKE) -C $(base_dir)/firrtl SBT="$(SBT)" root_dir=$(base_dir)/firrtl build-scala
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.SECONDARY: $(firrtl) $(firrtl_debug) $(verilog) $(verilog_debug)
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$(firrtl) $(params_file) $(generated_dir)/%.$(CONFIG).d: $(chisel_srcs)
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mkdir -p $(dir $@)
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cd $(base_dir) && $(SBT) "run $(PROJECT) $(MODEL) $(CONFIG) --targetDir $(generated_dir)"
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mv $(generated_dir)/$(MODEL).fir $(generated_dir)/$(MODEL).$(CONFIG).fir
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$(firrtl_debug) $(params_file_debug): $(chisel_srcs)
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mkdir -p $(dir $@)
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cd $(base_dir) && $(SBT) "run $(PROJECT) $(MODEL) $(CONFIG) --targetDir $(generated_dir_debug)"
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mv $(generated_dir_debug)/$(MODEL).fir $(generated_dir_debug)/$(MODEL).$(CONFIG).fir
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%.v: %.fir $(FIRRTL)
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mkdir -p $(dir $@)
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$(FIRRTL) $(patsubst %,-i %,$(filter %.fir,$^)) -o $@ -X verilog
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VERILATOR := verilator --cc --exe
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VERILATOR_FLAGS := --top-module $(MODEL) +define+PRINTF_COND=$(MODEL).reset --assert \
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-Wno-UNSIGNED -Wno-COMBDLY -Wno-MULTIDRIVEN -Wno-WIDTH -Wno-STMTDLY -Wno-SELRANGE -Wno-IMPLICIT
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cppfiles = $(addprefix $(base_dir)/csrc/, $(addsuffix .cc, $(CXXSRCS)))
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model_header = $(generated_dir)/$(MODEL).$(CONFIG)/V$(MODEL).h
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model_header_debug = $(generated_dir_debug)/$(MODEL).$(CONFIG)/V$(MODEL).h
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$(addsuffix .o,$(CXXSRCS)): %.o: $(base_dir)/csrc/%.cc $(base_dir)/csrc/*.h $(consts_header)
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$(CXX) $(CXXFLAGS) -DVERILATOR -I$(generated_dir) -c -o $@ $<
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$(addsuffix .debug.o,$(CXXSRCS)): %.debug.o: $(base_dir)/csrc/%.cc $(base_dir)/csrc/*.h $(consts_header_debug)
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$(CXX) $(CXXFLAGS) -DVERILATOR -I$(generated_dir_debug) -c -o $@ $<
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$(emu): $(verilog) $(cppfiles) libdramsim.a $(consts_header)
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mkdir -p $(generated_dir)/$(MODEL).$(CONFIG)
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$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(generated_dir)/$(MODEL).$(CONFIG) \
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-o $(abspath $(sim_dir))/$@ $< $(cppfiles) -LDFLAGS "$(LDFLAGS)" \
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-CFLAGS "$(CXXFLAGS) -DVERILATOR -I$(generated_dir) -include $(model_header) -include $(consts_header) -include $(scr_header)"
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$(MAKE) -C $(generated_dir)/$(MODEL).$(CONFIG) -f V$(MODEL).mk
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$(emu_debug): $(verilog_debug) $(cppfiles) libdramsim.a $(consts_header_debug) $(generated_dir)/$(MODEL).$(CONFIG).d
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mkdir -p $(generated_dir_debug)/$(MODEL).$(CONFIG)
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$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(generated_dir_debug)/$(MODEL).$(CONFIG) --trace \
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-o $(abspath $(sim_dir))/$@ $< $(cppfiles) -LDFLAGS "$(LDFLAGS)" \
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-CFLAGS "$(CXXFLAGS) -DVERILATOR -I$(generated_dir_debug) -include $(model_header_debug) -include $(consts_header_debug) -include $(scr_header_debug)"
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$(MAKE) -C $(generated_dir_debug)/$(MODEL).$(CONFIG) -f V$(MODEL).mk
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