Henry Cook
|
3a266cbbfa
|
final Reg changes
|
2013-08-15 15:28:15 -07:00 |
|
Henry Cook
|
b570435847
|
Reg standardization
|
2013-08-13 17:50:02 -07:00 |
|
Henry Cook
|
858169917e
|
removed dummy DNCs handled by pruning
|
2013-08-12 22:34:46 -07:00 |
|
Henry Cook
|
d9b3c7cfc8
|
Moved RenEn to ChiselUtil
|
2013-08-12 22:18:25 -07:00 |
|
Huy Vo
|
387cf0ebe0
|
reset -> resetVal, getReset -> reset
|
2013-08-12 20:51:54 -07:00 |
|
Henry Cook
|
1a9e43aa11
|
initial attempt at upgrade
|
2013-08-12 10:39:11 -07:00 |
|
Henry Cook
|
de313d97de
|
Merge branch 'master' of github.com:ucb-bar/riscv-rocket
|
2013-08-02 16:30:09 -07:00 |
|
Henry Cook
|
4eaab214d2
|
Fold uncore constants into TileLinkConfiguration, update coherence API
|
2013-08-02 16:29:51 -07:00 |
|
Henry Cook
|
bef6c1db35
|
minor nbdcache cleanup
|
2013-08-02 16:29:37 -07:00 |
|
Stephen Twigg
|
3132db4f90
|
Add stats PCR (cr28) to be used to flag whether a core is doing 'interesting' activity.
|
2013-07-30 16:36:28 -07:00 |
|
Henry Cook
|
9abdf4e154
|
Make compatible with scala 2.10. List.sort deprecated. Refactor constants into package object.
|
2013-07-23 20:27:58 -07:00 |
|
Henry Cook
|
5c00d0a030
|
new tilelink arbiter type
|
2013-07-09 15:31:46 -07:00 |
|
Andrew Waterman
|
7cc53c7725
|
clean up Str
|
2013-06-15 00:45:53 -07:00 |
|
Andrew Waterman
|
95c5147dc5
|
Add RISC-V instruction disassembler
|
2013-06-13 10:31:04 -07:00 |
|
Henry Cook
|
569d8fd796
|
Merge branch 'tilelink-data'
|
2013-05-23 14:14:40 -07:00 |
|
Henry Cook
|
12205b9684
|
remove obsolete config file reader prototype
|
2013-05-23 14:09:03 -07:00 |
|
Andrew Waterman
|
fe9adfe71b
|
Simplify and correct integer multiplier
|
2013-05-22 17:27:50 -07:00 |
|
Yunsup Lee
|
11133d6d4c
|
clock gate s2 registers in the frontend
|
2013-05-21 18:59:21 -07:00 |
|
Yunsup Lee
|
c837c1d800
|
fix bug in previous JALR commit
on commit tag 9a122c06d1bf11237d7fb0769d454a67bbb7400e
|
2013-05-21 18:28:44 -07:00 |
|
Henry Cook
|
69b508ff39
|
ported caches and htif to use new tilelink
|
2013-05-21 17:21:04 -07:00 |
|
Andrew Waterman
|
28f914c3f2
|
don't JALR to speculatively-bypassed addresses
Technically not necessary, but probably improves performance.
|
2013-05-21 16:56:58 -07:00 |
|
Yunsup Lee
|
dcde377303
|
Fix DM I$ deadlock
BTB predictions were causing infinite miss loops
|
2013-05-20 15:22:58 -07:00 |
|
Andrew Waterman
|
3a1b5f01b2
|
don't take interrupts while they're disabled!
a control bug allowed an interrupt to be taken on the instruction immediately
following an interrupt-disabling instruction (but not thereafter).
|
2013-05-19 23:27:47 -07:00 |
|
Andrew Waterman
|
6eb4c2542a
|
comment out I$ assert for now
|
2013-05-18 18:09:23 -07:00 |
|
Andrew Waterman
|
1dab984231
|
use UFix instead of Bits for arithmetic
|
2013-05-18 00:45:29 -07:00 |
|
Andrew Waterman
|
dfa7a03f73
|
use assert, not Assert
|
2013-05-18 00:45:13 -07:00 |
|
Andrew Waterman
|
d405ffa949
|
assume all I$ grants bear data
|
2013-05-01 21:01:20 -07:00 |
|
Andrew Waterman
|
474d321cc7
|
fix meta hazard counter to reset on new meta writes
|
2013-05-01 16:35:24 -07:00 |
|
Andrew Waterman
|
a6a88fce19
|
Revert "broaden scope of s1_nack to include new probes accepted by the probe unit on that cycle"
This reverts commit b41e6bc50519631ba097ac1196737be7107295f9.
|
2013-05-01 16:34:45 -07:00 |
|
Andrew Waterman
|
63a38e7982
|
Revert "temp"
This reverts commit 73705e6ed8f98d08ce6b30fbe760de694c6563ae.
|
2013-05-01 16:34:33 -07:00 |
|
Henry Cook
|
b6945408cb
|
temp
|
2013-05-01 10:24:36 -07:00 |
|
Henry Cook
|
722bc917d3
|
broaden scope of s1_nack to include new probes accepted by the probe unit on that cycle
|
2013-05-01 10:05:54 -07:00 |
|
Andrew Waterman
|
1501e90c1f
|
interlock probe unit on tag RAW hazards
|
2013-04-30 00:38:22 -07:00 |
|
Henry Cook
|
e8b20f3d38
|
clear meta state of silently-dropped, clean evictee, so as to prevent a write race on meta array between probes on evictee and refill grant
|
2013-04-25 17:41:04 -07:00 |
|
Andrew Waterman
|
50ccc20bf3
|
replace RDNPC with AUIPC
|
2013-04-22 04:20:15 -07:00 |
|
Henry Cook
|
db5a060c7d
|
fix io dir
|
2013-04-10 13:47:30 -07:00 |
|
Andrew Waterman
|
ae7720e284
|
guarantee LR/SC forward progress
the mechanism is to block new probes for several cycles after a successful LR.
this also cleans up the MSHR <-> ProbeUnit interface slightly.
|
2013-04-07 19:27:21 -07:00 |
|
Andrew Waterman
|
e74e032c87
|
simplify MSHR memory response logic
|
2013-04-06 01:03:37 -07:00 |
|
Andrew Waterman
|
1abb9277db
|
fix LR/SC atomicity violation
note, it's still not starvation-free.
|
2013-04-05 19:13:38 -07:00 |
|
Andrew Waterman
|
8cbdeb2abf
|
add LR/SC support
|
2013-04-04 17:07:09 -07:00 |
|
Andrew Waterman
|
fc46daecf6
|
don't flush pipeline on writes to side-effect-free PCRs
notably, K0, K1, and EPC
|
2013-04-04 17:07:09 -07:00 |
|
Andrew Waterman
|
8b439ef20d
|
only support setpcr/clearpcr of SR
the full PCR RMW support was wasted area/power
|
2013-04-04 17:07:08 -07:00 |
|
Andrew Waterman
|
d43f484feb
|
take interrupts on nonzero fromhost values
|
2013-04-04 17:07:08 -07:00 |
|
Andrew Waterman
|
d4a3351cfc
|
expose pending interrupts in status register
|
2013-04-04 17:07:08 -07:00 |
|
Henry Cook
|
f8aebcbf8c
|
fix for cache controller bug: failing to mux correct metadata into mshr.io.old_meta on tag match
|
2013-04-04 15:50:29 -07:00 |
|
Henry Cook
|
16113a96ba
|
fixes after merge
|
2013-03-25 19:09:08 -07:00 |
|
Henry Cook
|
95f0a688e9
|
Merge branch 'release-xacts'
Conflicts:
src/htif.scala
src/icache.scala
src/nbdcache.scala
src/tile.scala
|
2013-03-20 17:37:50 -07:00 |
|
Henry Cook
|
273bd34091
|
Generalized mem arbiter, moved to uncore. Support for multiple banks when acking grants.
|
2013-03-20 15:53:36 -07:00 |
|
Henry Cook
|
6d2541aced
|
nTiles -> nClients in LogicalNetworkConfig
|
2013-03-20 14:12:36 -07:00 |
|
Andrew Waterman
|
ea9d0b771e
|
remove aborts; simplify probes
|
2013-03-19 15:29:40 -07:00 |
|
Yunsup Lee
|
0f50970913
|
move HellaQueue to uncore
|
2013-03-19 00:43:20 -07:00 |
|
Henry Cook
|
e0361840bd
|
writebacks on release network pass asm tests and bmarks
|
2013-02-28 18:11:40 -08:00 |
|
Andrew Waterman
|
35349d227f
|
update to new Mem style
|
2013-02-20 16:09:46 -08:00 |
|
Andrew Waterman
|
9f89c812b7
|
fix HTIF memory size reporting
|
2013-01-29 23:08:25 -08:00 |
|
Yunsup Lee
|
a0bd0adeb2
|
change write/read port ordering for vlsi_mem_gen script
|
2013-01-29 21:32:42 -08:00 |
|
Andrew Waterman
|
66eb3720a4
|
fix SRAM semantics bug in HellaFlowQueue
|
2013-01-29 21:16:42 -08:00 |
|
Yunsup Lee
|
60bd3a6413
|
Revert "shuffled FPU control logic around to make functional unit retiming work better"
This reverts commit 20dd308067b143adff4913fc7ac710a393ca1d86.
|
2013-01-29 19:34:55 -08:00 |
|
Andrew Waterman
|
6275e009f8
|
fix HellaQueue deq.valid signal
|
2013-01-28 20:57:43 -08:00 |
|
Andrew Waterman
|
45d8066f45
|
add HellaQueue, an SRAM-based queue
|
2013-01-28 20:54:25 -08:00 |
|
Andrew Waterman
|
37c67f1d87
|
pipeline reset to the vector unit
|
2013-01-28 17:56:32 -08:00 |
|
Rimas Avizienis
|
f2df6147df
|
shuffled FPU control logic around to make functional unit retiming work better
|
2013-01-28 17:17:09 -08:00 |
|
Henry Cook
|
f5729c9f25
|
removed ack_required field from grant messages
|
2013-01-28 16:44:17 -08:00 |
|
Henry Cook
|
8cbd316b5e
|
Merge branch 'ready-sig-fix' into pin-cleanup
|
2013-01-27 23:04:58 -08:00 |
|
Henry Cook
|
931cffa749
|
ready signal fix
|
2013-01-27 23:04:35 -08:00 |
|
Henry Cook
|
83c207c852
|
pin cleanup in htif
|
2013-01-27 12:00:28 -08:00 |
|
Henry Cook
|
409b549d3c
|
actually cleared up tile ios
|
2013-01-27 11:27:09 -08:00 |
|
Henry Cook
|
696dd102eb
|
cleans up unconnected tile io pins (networking headers overwritten at top level)
|
2013-01-27 10:59:41 -08:00 |
|
Andrew Waterman
|
c890099e09
|
add System Control Register space to HTIF
|
2013-01-24 23:41:24 -08:00 |
|
Andrew Waterman
|
575bd3445a
|
re-generalize scoreboard
|
2013-01-24 18:00:39 -08:00 |
|
Andrew Waterman
|
1fbc20450e
|
don't allow simultaneous reads and writes to the tag ram
|
2013-01-24 17:55:00 -08:00 |
|
Andrew Waterman
|
37ee843b2c
|
don't use reset combinationally
|
2013-01-24 17:55:00 -08:00 |
|
Andrew Waterman
|
bb6fbddf1f
|
don't probe the mshr file to inquire about refills
|
2013-01-24 17:54:59 -08:00 |
|
Andrew Waterman
|
5b9f938263
|
correctly sign-extend badvaddr, epc, and ebase
|
2013-01-24 17:54:59 -08:00 |
|
Rimas Avizienis
|
63060bc0a8
|
minor tweaks for eos18 tapeout (SRAM r/w port ordering, etc)
|
2013-01-23 19:27:53 -08:00 |
|
Henry Cook
|
6b00e7ff74
|
New TileLink bundle names
|
2013-01-21 17:18:23 -08:00 |
|
Henry Cook
|
a2fa3fd04d
|
Refactored packet headers/payloads
|
2013-01-15 15:50:37 -08:00 |
|
Henry Cook
|
e1225c5114
|
standardize IO naming convention
|
2013-01-07 13:41:36 -08:00 |
|
Henry Cook
|
261e14f831
|
Refactored uncore conf
|
2013-01-07 13:41:36 -08:00 |
|
Andrew Waterman
|
78868f6075
|
add config option to trade mul/div area for speed
|
2013-01-06 03:47:17 -08:00 |
|
Andrew Waterman
|
ce9f4881d2
|
remove broken multiplier early out
|
2013-01-06 03:47:00 -08:00 |
|
Andrew Waterman
|
05f19b21d0
|
merge multiplier and divider
|
2012-12-12 02:22:47 -08:00 |
|
Andrew Waterman
|
c921fc34a9
|
merge ALU left and right shifters
|
2012-12-12 02:22:34 -08:00 |
|
Andrew Waterman
|
f5c53ce35d
|
add ecc support to d$ data rams
i haven't injected errors yet; it may well be incorrect.
|
2012-12-11 15:58:53 -08:00 |
|
Andrew Waterman
|
3f59e439ef
|
fix d$ tag raw hazard
|
2012-12-07 15:14:20 -08:00 |
|
Andrew Waterman
|
e9752f1d72
|
pipeline host pcr access
|
2012-12-06 14:22:07 -08:00 |
|
Andrew Waterman
|
4dda38204f
|
fix d$ reset bug
|
2012-12-06 03:13:22 -08:00 |
|
Andrew Waterman
|
290d3d226c
|
fix AMO and store bypass bugs
thanks, torture tester
|
2012-12-06 02:07:52 -08:00 |
|
Andrew Waterman
|
4608660f6e
|
torture revealed a couple bugs
FP loads/stores with certain negative offsets could cause illegal rounding
mode traps, and x's were cropping up in situations that are benign in HW.
|
2012-12-04 05:57:53 -08:00 |
|
Andrew Waterman
|
90cae54ac4
|
fix D$ read/write concurrency bug
|
2012-11-27 02:42:27 -08:00 |
|
Andrew Waterman
|
9c857b83f0
|
refactor PCR file
|
2012-11-27 01:28:06 -08:00 |
|
Andrew Waterman
|
64674d4d39
|
clean up PTW and support PADDR_BITS < VADDR_BITS
|
2012-11-26 20:38:45 -08:00 |
|
Andrew Waterman
|
608f65e716
|
don't wastefully read 2x the bits from D$ RAMs
|
2012-11-26 20:34:30 -08:00 |
|
Andrew Waterman
|
352bb464b5
|
clock gate X/M and M/W store data registers
|
2012-11-26 20:33:41 -08:00 |
|
Andrew Waterman
|
8a6ff5f9aa
|
fix D$ writeback bug
I swear I did this last week... perhaps I am finally losing it!
|
2012-11-25 19:46:48 -08:00 |
|
Andrew Waterman
|
de2f28193a
|
get rid of more global constants
|
2012-11-25 04:24:25 -08:00 |
|
Andrew Waterman
|
c036cdc1ea
|
add option for 2-cycle load-use delay
|
2012-11-24 22:01:08 -08:00 |
|
Andrew Waterman
|
b514c7b725
|
clean up I$ parity code
|
2012-11-24 22:00:43 -08:00 |
|
Andrew Waterman
|
55082e45c4
|
add AVec, which automatically infers element type
should consider modifying Vec as such
|
2012-11-24 18:19:28 -08:00 |
|
Andrew Waterman
|
2b26082132
|
use 1r1w ram for tags; merge tags & permissions
setting the dirty bit now allocates an MSHR (to reuse the existing datapath)
|
2012-11-20 04:09:26 -08:00 |
|
Andrew Waterman
|
72f94d1141
|
fix virtual address sign extension detection
|
2012-11-20 04:06:57 -08:00 |
|
Andrew Waterman
|
30038bda8a
|
bypass stores to subsequent loads
since we handle subword stores as RMW operations, this occurs frequently
|
2012-11-20 01:33:32 -08:00 |
|
Yunsup Lee
|
395e4e3dd6
|
andrew'x fix for D$ corner case in writeback->abort->probe
|
2012-11-18 03:11:06 -08:00 |
|
Yunsup Lee
|
06eeb90e2a
|
vector unit interfaces to the new D$
|
2012-11-17 20:07:41 -08:00 |
|
Yunsup Lee
|
81d711e892
|
fix D$ bug; now D$ doesn't respond to prefetches
|
2012-11-17 20:06:13 -08:00 |
|
Andrew Waterman
|
29bc361d6c
|
remove global constants; disentangle hwacha a bit
|
2012-11-17 17:24:08 -08:00 |
|
Andrew Waterman
|
5a7777fe4d
|
clock gate integer datapath more aggressively
|
2012-11-17 06:48:44 -08:00 |
|
Andrew Waterman
|
cc067026a2
|
pipeline D$ response -> FPU regfile
|
2012-11-17 06:48:11 -08:00 |
|
Andrew Waterman
|
e68b039133
|
fix misc. D$ control bugs
|
2012-11-17 06:47:27 -08:00 |
|
Andrew Waterman
|
dad7b71062
|
provide cmd/addr with cache response
|
2012-11-16 21:26:12 -08:00 |
|
Andrew Waterman
|
cb8ac73045
|
provide store data with cache response
|
2012-11-16 21:15:13 -08:00 |
|
Andrew Waterman
|
9e010beffe
|
fix D$ refill bug
|
2012-11-16 21:05:29 -08:00 |
|
Andrew Waterman
|
8dce89703a
|
new D$ with better QoR and AMO pipelining
Vector unit is disabled because nack handling needs to be fixed.
|
2012-11-16 02:39:33 -08:00 |
|
Andrew Waterman
|
a90a1790a5
|
improve tlb qor
|
2012-11-16 01:59:38 -08:00 |
|
Andrew Waterman
|
ff8c736d94
|
move icache invalidate out of request bundle
|
2012-11-16 01:55:45 -08:00 |
|
Andrew Waterman
|
6d10115b19
|
fix D$ tag width
|
2012-11-15 16:46:39 -08:00 |
|
Yunsup Lee
|
be1980dd2d
|
refactored vector queue interface
|
2012-11-07 01:15:33 -08:00 |
|
Yunsup Lee
|
8764fe786a
|
refactored vector tlb
|
2012-11-06 23:53:52 -08:00 |
|
Yunsup Lee
|
9a02298f6f
|
andrew's fix for tlb lockup
|
2012-11-06 23:52:58 -08:00 |
|
Andrew Waterman
|
4d1ca8ba3a
|
remove more global consts; refactor DTLBs
D$ now contains DTLB. provide full VAddr with initial request.
VU now has its own DTLBs.
|
2012-11-06 08:13:44 -08:00 |
|
Andrew Waterman
|
e76892f758
|
remove more global constants
|
2012-11-06 02:55:45 -08:00 |
|
Andrew Waterman
|
c5b93798fb
|
factor out more global constants
|
2012-11-05 23:52:32 -08:00 |
|
Yunsup Lee
|
ee081d1671
|
modify code to fix UFix := Bits error
|
2012-11-05 01:35:55 -08:00 |
|
Yunsup Lee
|
2a25307a8f
|
revamp the vector unit with the new frontend
|
2012-11-05 01:35:55 -08:00 |
|
Andrew Waterman
|
5b20ed71be
|
move rd=0 check into bypass logic
before, the check was in the write enable logic, but moving it obviated
an awkward corner case for mtpcr with rd=0.
|
2012-11-05 01:30:57 -08:00 |
|
Andrew Waterman
|
5e103054fd
|
fix bug in quine mccluskey
|
2012-11-05 00:28:25 -08:00 |
|
Andrew Waterman
|
e9eca6a95d
|
refactor I$ config; remove Top class
|
2012-11-04 16:59:36 -08:00 |
|
Andrew Waterman
|
7380c9fe60
|
aggressively clock gate int and fp datapaths
|
2012-11-04 16:40:14 -08:00 |
|
Andrew Waterman
|
bd2d61de03
|
use 8T SRAM for I$; gate clock more aggressively
|
2012-11-04 16:39:25 -08:00 |
|
Andrew Waterman
|
fedee6c67d
|
add generic error correcting codes
|
2012-10-30 01:03:47 -07:00 |
|
Andrew Waterman
|
5773cbb68a
|
rejigger htif to use UncoreConfiguration
|
2012-10-18 17:26:03 -07:00 |
|
Henry Cook
|
e2eb7ce8e9
|
Cleanup git incompetence
|
2012-10-16 16:54:58 -07:00 |
|
Henry Cook
|
88ac5af181
|
Merged consts-as-traits
|
2012-10-16 16:32:35 -07:00 |
|
Henry Cook
|
6cff1c13d8
|
Refer to traits moved to uncore, add UncoreConfiguration to top
|
2012-10-16 14:22:23 -07:00 |
|
Andrew Waterman
|
b9a2af697d
|
turn off HAVE_VEC as it's currently broken
the new I$/frontend needs to be integrated
|
2012-10-16 07:38:19 -07:00 |
|
Andrew Waterman
|
0a640f2cc6
|
make DecodeLogic deterministic (hopefully)
|
2012-10-16 04:51:21 -07:00 |
|
Andrew Waterman
|
5821900329
|
don't refetch from I$ if on same 16B block
|
2012-10-16 02:24:38 -07:00 |
|
Andrew Waterman
|
b955985b38
|
improve divider QoR
|
2012-10-16 02:24:38 -07:00 |
|
Andrew Waterman
|
197154c485
|
use BTB for JALR
|
2012-10-16 02:24:37 -07:00 |
|
Andrew Waterman
|
fc648d13a1
|
remove old Mux1H; add implicit conversions
|
2012-10-16 02:24:37 -07:00 |
|
Andrew Waterman
|
661f8e635b
|
merge I$, ITLB, BTB into Frontend
|
2012-10-16 02:24:37 -07:00 |
|
Andrew Waterman
|
fcd69dba98
|
add optional early-out to mul/div
|
2012-10-16 02:24:37 -07:00 |
|
Andrew Waterman
|
27ddff1adb
|
simplify and improve multiplier
|
2012-10-16 02:24:37 -07:00 |
|
Henry Cook
|
8970b635b2
|
improvements to implicit RocketConfiguration parameter
|
2012-10-15 16:29:49 -07:00 |
|
Henry Cook
|
a7a4e65690
|
Initial verison of reading config from files
|
2012-10-15 16:05:50 -07:00 |
|
Henry Cook
|
5d2a470215
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all rocket-specific arbiters in one file and refactored traits slightly
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2012-10-15 16:05:32 -07:00 |
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Huy Vo
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1864e41361
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memserdes + slowio out of rocket and into uncore
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2012-10-10 15:25:24 -07:00 |
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Huy Vo
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fe21142972
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fixed memdessert unpacking
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2012-10-09 13:03:17 -07:00 |
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Henry Cook
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9025d0610c
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first pass at configuration object passed as implicit parameter
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2012-10-07 22:37:29 -07:00 |
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Henry Cook
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dfdfddebe8
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constants as traits
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2012-10-07 22:20:03 -07:00 |
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Henry Cook
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b5ff436092
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decode constant object split into multiple objects
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2012-10-05 15:50:42 -07:00 |
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