Henry Cook
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5e26b4ab66
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Merge branch 'dse'
Conflicts:
src/main/scala/htif.scala
src/main/scala/llc.scala
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2014-09-06 06:16:58 -07:00 |
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Henry Cook
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5e2f98747f
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Merge branch 'dse'
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2014-09-06 06:10:15 -07:00 |
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Yunsup Lee
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1cb2d1d7b7
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initialize all SRAMs to avoid X propagation problem
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2014-09-04 11:06:01 -07:00 |
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Yunsup Lee
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763c57931b
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fix problem introduced with verilog generation in vsim/fsim
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2014-09-04 09:49:57 -07:00 |
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Scott Beamer
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6c6f5a3843
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add verilog target to build without simulator
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2014-09-03 17:28:45 -07:00 |
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Scott Beamer
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13b6ec4712
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including better sbt fixes
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2014-09-02 15:16:31 -07:00 |
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Scott Beamer
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f8821b4cc9
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better fix with explanation of sbt issue
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2014-09-02 15:16:03 -07:00 |
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Scott Beamer
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600c5d50a9
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better fix with explanation of sbt issue
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2014-09-02 15:14:56 -07:00 |
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Scott Beamer
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26649b30ed
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fixes sbt error during first run
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2014-09-02 14:34:55 -07:00 |
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Scott Beamer
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f9922a106b
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fixes sbt error during first run
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2014-09-02 14:34:36 -07:00 |
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Scott Beamer
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bfb662968d
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fixes sbt error during first run
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2014-09-02 14:33:58 -07:00 |
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Henry Cook
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82467313dd
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merge in rocketchip changes from master
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2014-09-02 13:51:57 -07:00 |
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Henry Cook
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3250db0dd5
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bump uncore
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2014-09-02 12:37:44 -07:00 |
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Henry Cook
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712f3a754d
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merge in master
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2014-09-02 12:34:42 -07:00 |
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Henry Cook
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8622eb0f5b
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bump rocket
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2014-09-01 13:34:15 -07:00 |
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Henry Cook
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b42a2ab40a
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Final parameter refactor
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2014-09-01 13:28:58 -07:00 |
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Adam Izraelevitz
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2d6aafc32e
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Merge branch 'dse' of github.com:ucb-bar/rocket-staging into HEAD
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2014-09-01 11:23:50 -07:00 |
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Yunsup Lee
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7734285507
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forgot to comment out hwacha
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2014-09-01 09:01:36 -07:00 |
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Yunsup Lee
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0d18e491c7
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update gitignore
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2014-09-01 08:59:59 -07:00 |
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Yunsup Lee
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882fecf43a
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update README
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2014-08-31 20:57:16 -07:00 |
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Yunsup Lee
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c03c09ec31
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update for rocket-chip release
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2014-08-31 20:26:55 -07:00 |
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Sagar Karandikar
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83c6c2c9e2
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rename refs to zynq-fpga to fpga-zynq
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2014-08-29 10:26:48 -07:00 |
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Henry Cook
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78ab83d224
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refactor fpga top/config
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2014-08-28 13:07:54 -07:00 |
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Scott Beamer
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83380053de
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use fpga backend for fpga
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2014-08-26 15:56:27 -07:00 |
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Henry Cook
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bf356b9cb4
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Refactor to combine fpga and vlsi tops, part 1
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2014-08-24 19:30:53 -07:00 |
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Henry Cook
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17b2359c9a
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htif parameters trait
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2014-08-24 19:27:58 -07:00 |
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Henry Cook
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a41d55b643
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Final parameter refactor.
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2014-08-23 01:26:03 -07:00 |
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Henry Cook
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dc5643b12f
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Final parameter refactor.
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2014-08-23 01:19:36 -07:00 |
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Scott Beamer
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63b62394d9
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added l2 to fpga
with new chisel & uncore, it goes into brams
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2014-08-20 15:41:07 -07:00 |
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Scott Beamer
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e384b33cc3
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don't generate a write mask for BigMem if it isn't used
not needed for llc data
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2014-08-19 15:50:20 -07:00 |
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Henry Cook
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9b36162b67
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Point rocket/ to rocket-staging repo
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2014-08-19 14:20:15 -07:00 |
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Henry Cook
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2741bbf2b9
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Point rocket/ to rocket-staging repo
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2014-08-19 13:53:24 -07:00 |
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Henry Cook
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6a4193cf90
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minor cache param cleanup
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2014-08-19 11:38:46 -07:00 |
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Henry Cook
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2de268b3b1
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Cache utility traits. Completely compiles, asm tests hang.
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2014-08-19 11:38:20 -07:00 |
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Henry Cook
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ca5f38ff26
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a few more fixes. some param lookups fail (here() in Alter blocks)
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2014-08-19 11:38:11 -07:00 |
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Henry Cook
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0dac9a7467
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Full conversion to params. Compiles but does not elaborate.
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2014-08-19 11:38:02 -07:00 |
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Adam Izraelevitz
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4e6d69892d
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Added initial brainstorm for parameter hierarchical flattening, does not compile ;)
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2014-08-19 11:37:50 -07:00 |
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Adam Izraelevitz
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812353bace
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Ported FPU parameters to new Chisel Parameters
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2014-08-19 11:37:27 -07:00 |
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Yunsup Lee
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4ac8e59b1f
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add .gitignore
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2014-08-18 19:27:50 -07:00 |
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Yunsup Lee
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d520846638
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add README and sbt files
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2014-08-18 19:23:10 -07:00 |
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Scott Beamer
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e1a4d12c65
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fix small typos in README
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2014-08-14 17:59:24 -07:00 |
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Henry Cook
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1563c1bb36
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Fixed cache params. Asm and bmark tests pass.
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2014-08-12 15:00:54 -07:00 |
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Henry Cook
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e26f8a6f6a
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Fix errors in derived cache params
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2014-08-12 14:55:44 -07:00 |
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Henry Cook
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910c886837
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bump chisel
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2014-08-12 14:53:19 -07:00 |
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Henry Cook
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74796868e7
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chisel bump
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2014-08-12 10:58:09 -07:00 |
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Henry Cook
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0ca24a5d91
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fix debug flags
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2014-08-12 10:35:39 -07:00 |
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Henry Cook
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7f07771600
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Cache utility traits. Completely compiles, asm tests hang.
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2014-08-11 18:37:10 -07:00 |
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Henry Cook
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9ab3a4262c
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Cache utility traits. Completely compiles, asm tests hang.
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2014-08-11 18:35:49 -07:00 |
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Henry Cook
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1983260e6f
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a few more fixes. some param lookups fail (here() in Alter blocks)
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2014-08-10 23:08:21 -07:00 |
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Henry Cook
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63bd0b9d2a
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Partial conversion to params. Compiles but does not elaborate. Rocket and uncore conversion complete. FPGA and VLSI config are identical. HwachaConfig and MemoryControllerConfig not yet removed.
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2014-08-08 12:27:47 -07:00 |
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