Andrew Waterman
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6275e009f8
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fix HellaQueue deq.valid signal
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2013-01-28 20:57:43 -08:00 |
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Andrew Waterman
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45d8066f45
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add HellaQueue, an SRAM-based queue
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2013-01-28 20:54:25 -08:00 |
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Andrew Waterman
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37c67f1d87
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pipeline reset to the vector unit
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2013-01-28 17:56:32 -08:00 |
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Rimas Avizienis
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f2df6147df
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shuffled FPU control logic around to make functional unit retiming work better
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2013-01-28 17:17:09 -08:00 |
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Henry Cook
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8cbd316b5e
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Merge branch 'ready-sig-fix' into pin-cleanup
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2013-01-27 23:04:58 -08:00 |
|
Henry Cook
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931cffa749
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ready signal fix
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2013-01-27 23:04:35 -08:00 |
|
Henry Cook
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83c207c852
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pin cleanup in htif
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2013-01-27 12:00:28 -08:00 |
|
Henry Cook
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409b549d3c
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actually cleared up tile ios
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2013-01-27 11:27:09 -08:00 |
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Henry Cook
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696dd102eb
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cleans up unconnected tile io pins (networking headers overwritten at top level)
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2013-01-27 10:59:41 -08:00 |
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Andrew Waterman
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c890099e09
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add System Control Register space to HTIF
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2013-01-24 23:41:24 -08:00 |
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Andrew Waterman
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575bd3445a
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re-generalize scoreboard
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2013-01-24 18:00:39 -08:00 |
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Andrew Waterman
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1fbc20450e
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don't allow simultaneous reads and writes to the tag ram
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2013-01-24 17:55:00 -08:00 |
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Andrew Waterman
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37ee843b2c
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don't use reset combinationally
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2013-01-24 17:55:00 -08:00 |
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Andrew Waterman
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bb6fbddf1f
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don't probe the mshr file to inquire about refills
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2013-01-24 17:54:59 -08:00 |
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Andrew Waterman
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5b9f938263
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correctly sign-extend badvaddr, epc, and ebase
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2013-01-24 17:54:59 -08:00 |
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Rimas Avizienis
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63060bc0a8
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minor tweaks for eos18 tapeout (SRAM r/w port ordering, etc)
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2013-01-23 19:27:53 -08:00 |
|
Henry Cook
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6b00e7ff74
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New TileLink bundle names
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2013-01-21 17:18:23 -08:00 |
|
Henry Cook
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a2fa3fd04d
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Refactored packet headers/payloads
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2013-01-15 15:50:37 -08:00 |
|
Henry Cook
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e1225c5114
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standardize IO naming convention
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2013-01-07 13:41:36 -08:00 |
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Henry Cook
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261e14f831
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Refactored uncore conf
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2013-01-07 13:41:36 -08:00 |
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Andrew Waterman
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78868f6075
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add config option to trade mul/div area for speed
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2013-01-06 03:47:17 -08:00 |
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Andrew Waterman
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ce9f4881d2
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remove broken multiplier early out
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2013-01-06 03:47:00 -08:00 |
|
Andrew Waterman
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05f19b21d0
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merge multiplier and divider
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2012-12-12 02:22:47 -08:00 |
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Andrew Waterman
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c921fc34a9
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merge ALU left and right shifters
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2012-12-12 02:22:34 -08:00 |
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Andrew Waterman
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f5c53ce35d
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add ecc support to d$ data rams
i haven't injected errors yet; it may well be incorrect.
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2012-12-11 15:58:53 -08:00 |
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Andrew Waterman
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3f59e439ef
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fix d$ tag raw hazard
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2012-12-07 15:14:20 -08:00 |
|
Andrew Waterman
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e9752f1d72
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pipeline host pcr access
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2012-12-06 14:22:07 -08:00 |
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Andrew Waterman
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4dda38204f
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fix d$ reset bug
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2012-12-06 03:13:22 -08:00 |
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Andrew Waterman
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290d3d226c
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fix AMO and store bypass bugs
thanks, torture tester
|
2012-12-06 02:07:52 -08:00 |
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Andrew Waterman
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4608660f6e
|
torture revealed a couple bugs
FP loads/stores with certain negative offsets could cause illegal rounding
mode traps, and x's were cropping up in situations that are benign in HW.
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2012-12-04 05:57:53 -08:00 |
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Andrew Waterman
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90cae54ac4
|
fix D$ read/write concurrency bug
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2012-11-27 02:42:27 -08:00 |
|
Andrew Waterman
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9c857b83f0
|
refactor PCR file
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2012-11-27 01:28:06 -08:00 |
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Andrew Waterman
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64674d4d39
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clean up PTW and support PADDR_BITS < VADDR_BITS
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2012-11-26 20:38:45 -08:00 |
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Andrew Waterman
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608f65e716
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don't wastefully read 2x the bits from D$ RAMs
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2012-11-26 20:34:30 -08:00 |
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Andrew Waterman
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352bb464b5
|
clock gate X/M and M/W store data registers
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2012-11-26 20:33:41 -08:00 |
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Andrew Waterman
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8a6ff5f9aa
|
fix D$ writeback bug
I swear I did this last week... perhaps I am finally losing it!
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2012-11-25 19:46:48 -08:00 |
|
Andrew Waterman
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de2f28193a
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get rid of more global constants
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2012-11-25 04:24:25 -08:00 |
|
Andrew Waterman
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c036cdc1ea
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add option for 2-cycle load-use delay
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2012-11-24 22:01:08 -08:00 |
|
Andrew Waterman
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b514c7b725
|
clean up I$ parity code
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2012-11-24 22:00:43 -08:00 |
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Andrew Waterman
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55082e45c4
|
add AVec, which automatically infers element type
should consider modifying Vec as such
|
2012-11-24 18:19:28 -08:00 |
|
Andrew Waterman
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2b26082132
|
use 1r1w ram for tags; merge tags & permissions
setting the dirty bit now allocates an MSHR (to reuse the existing datapath)
|
2012-11-20 04:09:26 -08:00 |
|
Andrew Waterman
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72f94d1141
|
fix virtual address sign extension detection
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2012-11-20 04:06:57 -08:00 |
|
Andrew Waterman
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30038bda8a
|
bypass stores to subsequent loads
since we handle subword stores as RMW operations, this occurs frequently
|
2012-11-20 01:33:32 -08:00 |
|
Yunsup Lee
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395e4e3dd6
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andrew'x fix for D$ corner case in writeback->abort->probe
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2012-11-18 03:11:06 -08:00 |
|
Yunsup Lee
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06eeb90e2a
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vector unit interfaces to the new D$
|
2012-11-17 20:07:41 -08:00 |
|
Yunsup Lee
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81d711e892
|
fix D$ bug; now D$ doesn't respond to prefetches
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2012-11-17 20:06:13 -08:00 |
|
Andrew Waterman
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29bc361d6c
|
remove global constants; disentangle hwacha a bit
|
2012-11-17 17:24:08 -08:00 |
|
Andrew Waterman
|
5a7777fe4d
|
clock gate integer datapath more aggressively
|
2012-11-17 06:48:44 -08:00 |
|
Andrew Waterman
|
cc067026a2
|
pipeline D$ response -> FPU regfile
|
2012-11-17 06:48:11 -08:00 |
|
Andrew Waterman
|
e68b039133
|
fix misc. D$ control bugs
|
2012-11-17 06:47:27 -08:00 |
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