riscv/rocket-chip
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Author SHA1 Message Date
Megan WachsandGitHub f0a59a81c8 Merge pull request #783 from freechipsproject/plusarg_docstring 
plusarg_reader : Add the ability to add a documentation string.
 2017-06-05 18:21:07 -07:00
Megan Wachs 8d2e9a8631 Merge remote-tracking branch 'origin/master' into plusarg_docstring 2017-06-05 17:23:44 -07:00
Megan WachsandGitHub 7afd5e6070 remove unnecessary whitespace. Fix grammar. 2017-06-05 16:18:57 -07:00
Megan Wachs 8440c4b1c4 plusarg_reader : Add the ability to add a documentation string. 2017-06-05 16:16:52 -07:00
Megan WachsandGitHub 8d04e0efb8 Merge pull request #771 from freechipsproject/jtag_vpi_tab 
JTAG VPI: Make it work without debug_pp flag
 2017-05-30 17:29:23 -07:00
Megan Wachs 6aa13b4e01 JTAG VPI: Make it work without debug_pp flag 2017-05-30 15:46:45 -07:00
Megan WachsandGitHub f61e30763f Merge pull request #768 from freechipsproject/flush_jtag_vpi 
jtag_vpi: Attempt to more aggressively flush the simulator output
 2017-05-26 15:51:43 -07:00
Megan Wachs 0493372027 jtag_vpi: Attempt to more aggressively flush the simulator output as it is needed by other listeners 2017-05-26 11:48:45 -07:00
Megan WachsandWesley W. Terpstra 24a533e77c debug: Bump riscv-tools to pick up correction in gdbserver 2017-05-18 18:46:46 -07:00
Megan WachsandWesley W. Terpstra 304e82486f Debug: Update makefile now that OpenOCD is part of riscv-tools 2017-05-18 18:46:46 -07:00
Megan WachsandWesley W. Terpstra 26194b3078 bump riscv-tools to pick up latest version of debug tests 2017-05-18 18:46:45 -07:00
Megan WachsandGitHub d8996ea85f Empty commit to force travis 2017-05-16 22:56:58 -07:00
Megan WachsandGitHub f8c92d2669 Merge branch 'master' into pipeline-mmio 2017-05-03 08:37:12 -07:00
Megan Wachs 922a8ef5e0 local_interrupts: Correct off-by-1 if there is no SEIP 2017-05-02 21:55:25 -07:00
Megan WachsandGitHub d67738204f Interrupts: Less Pessimistic Synchronization (#714) 
* interrupts: Less pessimistic synchronization for the different interrupt types. There are some issues with the interrupt number assignments.

* interrupts: Allow an option to NOT synchronize all the external interrupts coming into PLIC

* interrupts: ExampleRocketChipTop uses PeripheryAsyncExtInterrupts. Realized 'abstract' doesn't do what I thought in Scala.

* interrupts: use consistent async/periph/core ordering

* interrupts: Properly condition on 0 External interrupts

* interrupts: CLINT is also synchronous to periph clock
 2017-04-28 14:49:24 -07:00
Megan Wachs 7ad4cc36f7 debug: Prevent writes to DATA/PROGBUF when busy 2017-04-26 11:11:21 -07:00
Megan WachsandAndrew Waterman e9db531e81 point to riscv-tools README for dependencies (#705) 
As pointed out, if we just point to 'master' branch, then people wouldn't get the correct list of dependencies.
 2017-04-25 20:20:27 -07:00
Megan Wachs c72b15f2a0 Down with any require() statement that makes me RTFC 2017-04-21 15:44:42 -07:00
Megan Wachs 9002e7e532 debug: Debug Module needs to handle DMI NOPs even if DTM won't send them. 2017-04-20 10:19:50 -07:00
Megan Wachs cc7f0a5b7a debug: whitespace cleanup 2017-04-20 10:19:50 -07:00
Megan Wachs 5934779082 debug: Clean up ValidReg assertion. 2017-04-20 10:19:50 -07:00
Megan Wachs 0c013a56c0 debug: Make DMI NOPs really NOPs. 
This simplifies SW design and CDC issues.
 2017-04-20 10:19:50 -07:00
Megan Wachs 1be13d6b4c PLIC: To avoid hazard between enable -> claim, enforce concurrency=1 2017-04-19 21:37:37 -07:00
Megan Wachs 3dfd584075 regmapper: remove the Pipe in the RegMapper Queue 
With this pipe here, devices which declare concurrency > 0
actually accept transactions on the same cycle they complete
the previous one. This is unexpected behavior.
 2017-04-19 21:37:37 -07:00
Megan WachsandGitHub 408107447c debug: DMI response should be busy, not zero, when there is an error. (#685) 2017-04-18 21:41:52 -07:00
Megan WachsandYunsup Lee 9cf86fa105 debug: checkpoint pointing to riscv-tools that picks up some tweaks in the debug riscv-tests 2017-04-17 10:28:33 -07:00
Megan WachsandYunsup Lee 9a6e7afc93 debug: bump OpenOCD to latest version of newprogram (with Examined RISC-V core message) 2017-04-17 10:28:33 -07:00
Megan WachsandYunsup Lee af6b2d8051 debug: DATA Region has to be aligned for ld/sd to correctly detect 64-bit cores. 2017-04-17 10:28:33 -07:00
Megan WachsandYunsup Lee b44d5f9386 debug: correctly consider .transfer bit in COMMAND 2017-04-17 10:28:33 -07:00
Megan WachsandYunsup Lee 79477fbea6 debug: Properly consider 'transfer' bit 2017-04-17 10:28:33 -07:00
Megan WachsandYunsup Lee 2dc4be6294 debug: remove preexec. Simplify the state machine since you can always just 'execute' once. 2017-04-17 10:28:33 -07:00
Megan WachsandYunsup Lee c5cb8b714f debug: Bump version and location of OpenOCD to pick up fix for off-by-1 in hartsel 2017-04-17 10:28:33 -07:00
Megan WachsandAndrew Waterman fd7f4a4c0f jtag: make it easier to assign MFR ID externally 2017-04-14 01:03:11 -07:00
Megan WachsandAndrew Waterman bef88c4c30 Add pointers to package dependencies to README (#670) 
Tell people where to look to find package dependency information
 2017-04-11 19:54:46 -07:00
Megan WachsandAndrew Waterman 051acee76c Debug: Fix off-by-1 for detecting nonexistent harts. 2017-04-07 16:47:16 -07:00
Megan WachsandAndrew Waterman 01372e1686 use Wire() correctly to assign a value 2017-04-07 16:47:16 -07:00
Megan WachsandAndrew Waterman 9ae4838708 jtag: Get rid of chisel deprecation warnings 2017-04-07 16:47:16 -07:00
Megan WachsandAndrew Waterman 22c6f728c3 debug: Use flags for resume instead of program buffer. Untested. 2017-04-07 16:47:16 -07:00
Megan WachsandAndrew Waterman d361e9e343 debug: temporarily leave preexec in place 2017-04-07 16:47:16 -07:00
Megan WachsandAndrew Waterman 0e2c34b0d6 debug: update register map with new spec 2017-04-07 16:47:16 -07:00
Megan WachsandGitHub df5caba7bf debug: Make it easier to override parts of the Default Debug Config (#655) 
* Handle single-step with a pipeline stall, not a flush

The pipeline flush approach broke when I changed the pipeline stage
the flush happens from

* debug: Make it easier to override parts of the Default Debug Config

* Fix typo in Debug code generation

abstractGeneratedI should be abstractGeneratedS when pulling out the opcode.
This doesn't actually break anything, but fix it for clarity.
 2017-04-06 10:33:17 -07:00
Megan WachsandAndrew Waterman c5b0b6fb85 debug: bump openOCD version to pick up read_mem fix. Use MemTest64 instead because it's more likely to fail than SimpleS0Test 2017-04-05 15:14:32 -07:00
Megan WachsandAndrew Waterman 2601740542 debug: fix some typos related to the ID->SEL mapping functions 2017-04-05 15:14:32 -07:00
Megan WachsandAndrew Waterman b94f1f15b0 debug: redirect DMI NOPs to CONTROL register so things don't hang during reset 2017-04-05 15:14:32 -07:00
Megan WachsandAndrew Waterman eef05cc1fc debug: Enforce mapping between hartsel and hartid, use more reasonable defaults for DATA and PROGBUF sizes. 2017-04-05 15:14:32 -07:00
Megan WachsandGitHub 629e9a2ef6 debug: Put DebugROM back inside the overall Debug Module (#647) 2017-04-03 16:36:53 -07:00
Megan WachsandGitHub d2c1bdc2ce Debug Controls (#639) 
* debug: Bump OpenOCD version to one that drives resets and sets cmderr appropriately.

* debug: Export the dmactive and ndreset signals to the top level and drive reset as intended in the TestHarness.
 2017-04-03 13:31:35 -07:00
Megan Wachs dec567ab0c Resturn riscv-tools to the priv 1.10 branch vs the pre-merge Debug v013 version. 2017-03-30 20:22:54 -07:00
Megan Wachs 0828ebe911 debug_v013: bump fesvr to use autoexec feature for memory writes. 2017-03-30 11:46:28 -07:00
Megan Wachs 9de06f8c83 Merge remote-tracking branch 'origin/master' into debug_v013_pr 2017-03-30 08:01:11 -07:00
Megan Wachs a14b7b5794 debug_v013: bump riscv-tools for slightly more efficient FESVR 2017-03-29 21:42:36 -07:00
Megan Wachs 24509fc69f debug_v013: Bump FESVR to pick up minor off-by-1 in error printing code. 2017-03-29 15:20:07 -07:00
Megan Wachs d8033b20fc Merge remote-tracking branch 'origin/master' into debug_v013_pr 2017-03-29 14:58:04 -07:00
Megan Wachs f6e72a3ef6 debug: Bump riscv-tools to pick up FESVR to version that works with debug v013 2017-03-29 14:46:06 -07:00
Megan Wachs 375a039279 debug: Use proper write-1-to-clear ABSTRACTCS.cmderr behavior (because fesvr code is using correct spec) 2017-03-28 21:14:22 -07:00
Megan Wachs ca9a5a1cf7 debug: Fixes in how the SimDTM was hooked up to FESVR 2017-03-28 21:13:45 -07:00
Megan Wachs ff38ebdf5e debug: Bump FESVR version to initial Debug v13. Doesn't work yet. 2017-03-28 21:12:57 -07:00
Megan Wachs d6ab929c41 debug: Remove older version of JTAG interface as it is superseded by the one in jtag package. 2017-03-27 21:25:37 -07:00
Megan Wachs cbc8d2400a debug: remove old Verilog DebugTransportModuleJtag file as it has been replaced by Chisel version 2017-03-27 21:24:44 -07:00
Megan Wachs bb64c92906 csr: Bring functionality in line with v13 spec. ebreak does not cause exception in Debug Mode, it just starts at Debug ROM again. 2017-03-27 21:21:48 -07:00
Megan Wachs 42ca597478 debug: Breaking change until FESVR is updated as well. 
* Replace v11 Debug Module with v13 module.
* Correct all instantiating interfaces.
* Rename "Debug Bus" to "DMI" (Debug
  Module Interface)
* Use Diplomacy interrupts for DebugInterrupt
* Seperate device for TLDebugROM
 2017-03-27 21:19:08 -07:00
Megan Wachs 43804726ac tilelink2: more helpful requirement message 2017-03-27 21:05:05 -07:00
Megan Wachs 0c3d85b52b debug: add generated ROM contents and register fields. 2017-03-27 21:01:36 -07:00
Megan Wachs 877e1cfba1 debug: add scripts to generate v13 Debug ROM contents. 2017-03-27 20:51:54 -07:00
Megan WachsandAndrew Waterman ab300f7985 Update README_TRAVIS.md 2017-03-27 17:45:50 -07:00
Megan WachsandAndrew Waterman 3fc74f3d08 Create README_TRAVIS.md 2017-03-27 17:45:46 -07:00
Megan WachsandGitHub 861651587b debug: Update Makefile to use new OpenOCD and allow for easier debugging. (#619) 2017-03-27 15:52:04 -07:00
Megan WachsandGitHub 7014263c29 Update LICENSE.SiFive (#618) 
Bump the year for the SiFive license
 2017-03-27 14:55:28 -07:00
Megan WachsandWesley W. Terpstra 70fa10fc55 Util: Add ResetCatchAndSync for synchronous deassert of Async Reset (#615) 2017-03-27 03:29:07 -07:00
Megan WachsandWesley W. Terpstra 08c4f7cea6 RocketTile: Create a wrapper for SyncRocketTile as well (#616) 
* RocketTile: Create a wrapper for SyncRocketTile as well

There is no guarantee that debugInterrupt is synchronous
to tlClk, even though it is true in the current implementation.
It will not be true in future implementations, as decoupling
this allows the debugInterrupt to be asserted across tlClk
gating/reset scenarios.

Therefore, even for SyncRocketTile, the debug interrupt needs to be
synchronized to coreClk, and for RationalRocketTile, 1 cycle
of synchronization is not sufficient.

Even though other interrupts may be synchronized, we just
synchronize them all to simplify the code at the expense of
a few cycles latency.

It could still be nice to use a parameter vs hard coding "3".

* RocketTile: Actually use the SyncRocketTile wrapper to get properly synchronized resets.
 2017-03-27 02:45:37 -07:00
Megan Wachs 11507ac7d6 TLROM: Use Resource as a parameter rather than assuming SimpleDevice. 
This allows more flexibility e.g. considering the ROM as part of other
devices.
 2017-03-26 20:58:14 -07:00
Megan Wachs bf648514e3 TLROM: allow name and compatibility strings to be provided by subclasses. 2017-03-26 20:58:14 -07:00
Megan WachsandGitHub 8e6beb80be Add ucb-art/chisel-jtag (#612) 
* jtag: Add ucb-art/chisel-jtag to junctions.

* jtag: Add missing Utils file for Tristate and NegativeEdgeLatch

* jtag: move to a top-level package
 2017-03-26 18:03:21 -07:00
Megan WachsandWesley W. Terpstra dcc9827ab4 Rename Prci.scala to Clint.scala (#591) 
The internals of this were renamed to CoreplexLocalInterrupter, so changing the top level name to match.
 2017-03-17 15:36:10 -07:00
Megan WachsandGitHub 4fe75965a0 Merge pull request #518 from ucb-bar/dtm_regression 
jtag_dtm: Update regression to run and pass.
 2017-01-18 14:39:53 -08:00
Megan Wachs e22b01a6fa jtag_dtm: Update regression to run and pass. 2017-01-18 12:08:13 -08:00
Megan WachsandWesley W. Terpstra 5090ff945b DebugModule: Be more paranoid about addressing corner cases. 2016-10-31 11:42:13 -07:00
Megan WachsandWesley W. Terpstra 10d084b9f3 DebugModule: Use the power of RegisterRouter to simplify the DebugROM code. 2016-10-31 11:41:18 -07:00
Megan WachsandWesley W. Terpstra af924d8c51 DebugModule: Instantiate TL2 DebugModule in BaseCoreplex 2016-10-31 11:41:18 -07:00
Megan WachsandWesley W. Terpstra d530ef7236 DebugModule: translate to TL2 with {32,64}-bit XLen width 2016-10-31 11:41:18 -07:00
Megan Wachs fd2d48acda lazy_module: If the user actually specifies a name, just use it without appending module name. 2016-10-25 15:58:09 -07:00
mwachs5andGitHub 3a1d8fe482 debug: use a different form of the crossing which doesn't create an AsyncScope (#394) 2016-10-09 20:33:18 -07:00
mwachs5andGitHub b5d4b72313 register_crossing: Remove the need for AsyncScope by specifying the master clock and reset. (#393) 2016-10-09 15:51:23 -07:00
mwachs5andGitHub a84a961a39 async_queue: Give names to all the registers which show up in the queue (#390) 
This is to aid debugging but even more so for backend constraint writers, who generally
need predictable names for registers to set false paths, etc.
 2016-10-08 17:50:50 -07:00
mwachs5andGitHub 4c49fef242 Merge pull request #388 from ucb-bar/cp-safer-crossings 
tilelink2: split isolation gates by direction
 2016-10-07 13:45:23 -07:00
mwachs5andWesley W. Terpstra e952f8f222 asyncqueue: Fix typo in the Async Queue (#381) 
* asyncqueue: Fix typo in the Async Queue that would cause the sync depth to be one less than expected.

* asyncqueue: Typo in the typo fix
 2016-10-04 21:02:06 -07:00
mwachs5andGitHub 784f0cf0b6 Merge pull request #370 from ucb-bar/move_clint_and_plic 
clint & plic: Move the default addresses
 2016-10-01 16:18:54 -07:00
Megan Wachs 28eba9b5ac clint/plic: Move the default addresses 2016-10-01 15:46:55 -07:00
mwachs5andGitHub 9a381e88d1 Suggest sane names for common objects (#369) 
* Suggest sane names for common objects frequently instantiated with factory methods

* Suggest names for common primitives using more Scala-esque Options
 2016-09-30 16:19:25 -07:00
Megan WachsandAndrew Waterman 1e43512142 jtag: Actually apply the sticky bits 2016-09-29 13:49:34 -07:00
Megan WachsandAndrew Waterman a4b81aebe0 jtag: Apply sticky bits for error and busy according to the current Debug Spec 2016-09-29 13:49:26 -07:00
Megan WachsandAndrew Waterman fc4d6ed0c6 jtag: clean up debug flags in regression/Makefile 2016-09-29 13:49:21 -07:00
Megan WachsandAndrew Waterman 45bd63fcc6 jtag: Prevent Debug RAM accesses from wrapping around, and bring the DTM closer to the Debug Spec 2016-09-29 13:49:14 -07:00
Megan WachsandAndrew Waterman 449d689a4e jtag: Connect the JTAG DTM side of the synchronizer! 2016-09-29 13:48:55 -07:00
mwachs5andGitHub f9e0a7ac24 Merge branch 'master' into async_register_crossing 2016-09-27 15:54:34 -07:00
Megan Wachs 3ce08f40a5 crossing: Remove reset from the logic in Register Crossing because it is no longer needed when the underlying crossings are asynchronously reset. Update the order of operations 2016-09-27 13:36:28 -07:00
mwachs5andGitHub 77a0f76289 Cleanup jtag dtm (#342) 
* debug: Clean up Debug TransportModule synchronizer

With async reset async queues, I feel its safe/cleaner
to remove the one-off "AsyncMailbox verilog black-box
and use the common primitive.

I also added some comments about correct usage of this
block. Probably the 'TRST' signal should be renamed
to make it less confusing, as it requires some processing
of the real JTAG 'TRST' signal.
 2016-09-26 11:10:27 -07:00
mwachs5andGitHub 8641639873 Async rst async queue (#336) 
* crossing: use async reset

* crossings: asyncqueue needs Asynchronous reset.

* crossing: Actually enable the head of the synchronizer flop chain

* crossing: remove reset from logic. This flop will no longer be written during reset because valid will be low.

* crossing: Tidy up code  & comments
 2016-09-26 11:08:38 -07:00
mwachs5andYunsup Lee 9acb352cf6 Correct Merge Conflitct -- clock, not clk (#327) 
I think there was a merge conflict somewhere. This should be 'clock', not 'clk'
 2016-09-21 20:02:01 -07:00
mwachs5andAndrew Waterman 3a809b209f Allow Makefile override of RESET_DELAY (#322) 2016-09-21 18:28:30 -07:00