Merge branch 'master' into async_register_crossing

src/main/scala/rocketchip/Configs.scala

@@ -195,3 +195,15 @@ class WithJtagDTM extends Config (
     case _ => throw new CDEMatchError
   }
 )
+
+class WithNoPeripheryArithAMO extends Config (
+  (pname, site, here) => pname match {
+    case PeripheryBusKey => PeripheryBusConfig(arithAMO = false, beatBytes = 4)
+  }
+)
+
+class With64BitPeriphery extends Config (
+  (pname, site, here) => pname match {
+    case PeripheryBusKey => PeripheryBusConfig(arithAMO = true, beatBytes = 8)
+  }
+)

src/main/scala/uncore/tilelink2/Bundles.scala

@@ -2,8 +2,8 @@
 
 package uncore.tilelink2
 
-import chisel3._
-import chisel3.util._
+import Chisel._
+import chisel3.util.{Irrevocable, IrrevocableIO}
 
 abstract class GenericParameterizedBundle[T <: Object](val params: T) extends Bundle
 {

src/main/scala/uncore/tilelink2/Fuzzer.scala

@@ -2,7 +2,6 @@
 package uncore.tilelink2
 
 import Chisel._
-import chisel3.util.LFSR16
 import unittest._
 import util.Pow2ClockDivider
 

src/main/scala/uncore/tilelink2/RAMModel.scala

@@ -3,7 +3,6 @@
 package uncore.tilelink2
 
 import Chisel._
-import chisel3.util.LFSR16
 
 // We detect concurrent puts that put memory into an undefined state.
 // put0, put0Ack, put1, put1Ack => ok: defined

src/main/scala/uncore/tilelink2/RegMapper.scala

@@ -2,8 +2,8 @@
 
 package uncore.tilelink2
 
-import chisel3._
-import chisel3.util._
+import Chisel._
+import chisel3.util.{Irrevocable, IrrevocableIO}
 
 // A bus agnostic register interface to a register-based device