riscv/rocket-chip
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53a02a62c8
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70 Commits

Author SHA1 Message Date
Christopher Celio
53a02a62c8 [commitlog] Fix sp/dp bug in FPU writeback 2015-09-15 16:46:47 -07:00
Christopher Celio
d630a03857 [commitlog] Added FP instructions to the commitlog 2015-09-15 15:59:13 -07:00
Andrew Waterman
78b2e947de Chisel3 compatibility fixes 2015-09-11 15:43:07 -07:00
Andrew Waterman
1718333f83 Don't use Vec as lvalue 2015-08-05 15:29:33 -07:00
Andrew Waterman
546205b174 Chisel3 compatibility: use >>Int instead of >>UInt 2015-08-05 15:29:03 -07:00
Andrew Waterman
6c0e1e33ab Purge UInt := SInt assignments 2015-07-31 15:42:10 -07:00
Andrew Waterman
57930e8a26 Chisel3 compatibility potpourri 2015-07-30 23:53:02 -07:00
Andrew Waterman
049fc8dc24 Chisel3 compatibility: use BitPat for don't-cares 
This one's hella ugly, but for the time being, idgaf.
 2015-07-28 02:48:49 -07:00
Andrew Waterman
ae73e3a997 Only instantiate div/sqrt unit if requested 2015-07-22 22:18:18 -07:00
Andrew Waterman
cc447c8110 Refactor pipeline RTL (merge ctrl + dpath into rocket) 2015-07-21 17:10:56 -07:00
Andrew Waterman
ac6e73e317 Add Wire() wrap 2015-07-15 20:24:18 -07:00
Andrew Waterman
be2ff6dec7 Vec(Reg) -> Reg(Vec) 2015-07-15 12:33:46 -07:00
Andrew Waterman
9ade0e41cc Integrate divide/sqrt unit 2015-04-04 16:39:17 -07:00
Yunsup Lee
8abf62fae3 add LICENSE 2014-09-12 18:06:41 -07:00
Adam Izraelevitz
812353bace Ported FPU parameters to new Chisel Parameters 2014-08-19 11:37:27 -07:00
Andrew Waterman
4ca152b012 Use BundleWithConf to avoid clone method boilerplate 2014-05-09 19:37:16 -07:00
Andrew Waterman
5996418021 Fix exception behavior of fmin/fmax 2014-03-18 18:36:51 -07:00
Andrew Waterman
a0389645b7 New FP encoding; improved FP implementation 2014-03-11 18:58:24 -07:00
Andrew Waterman
00bc1a2293 Add fclass.{s|d} instructions 2014-03-10 16:59:24 -07:00
Andrew Waterman
c7110c8389 Make FPU pipeline depths configurable 2014-02-28 13:39:59 -08:00
Andrew Waterman
95de358a96 More of the same FPU fix 
some SP ops followed by DP stores were not working because they
were encoded as subnormals, not NaNs.
 2014-01-17 14:09:30 -08:00
Andrew Waterman
cf38001e98 Fix fmv.s.x -> fsd 2014-01-17 03:52:35 -08:00
Andrew Waterman
924261e2b2 Update to new privileged ISA... phew 2013-11-25 04:35:15 -08:00
Andrew Waterman
1d2f4f8437 New ISA encoding, AUIPC semantics 2013-09-21 06:32:40 -07:00
Andrew Waterman
18968dfbc7 Move store data generation into cache 2013-09-14 16:15:07 -07:00
Andrew Waterman
d4a0db4575 Reflect ISA changes 2013-08-24 14:43:55 -07:00
Henry Cook
3a266cbbfa final Reg changes 2013-08-15 15:28:15 -07:00
Henry Cook
b570435847 Reg standardization 2013-08-13 17:50:02 -07:00
Henry Cook
d9b3c7cfc8 Moved RenEn to ChiselUtil 2013-08-12 22:18:25 -07:00
Henry Cook
1a9e43aa11 initial attempt at upgrade 2013-08-12 10:39:11 -07:00
Henry Cook
9abdf4e154 Make compatible with scala 2.10. List.sort deprecated. Refactor constants into package object. 2013-07-23 20:27:58 -07:00
Yunsup Lee
60bd3a6413 Revert "shuffled FPU control logic around to make functional unit retiming work better" 
This reverts commit 20dd308067b143adff4913fc7ac710a393ca1d86.
 2013-01-29 19:34:55 -08:00
Rimas Avizienis
f2df6147df shuffled FPU control logic around to make functional unit retiming work better 2013-01-28 17:17:09 -08:00
Henry Cook
e1225c5114 standardize IO naming convention 2013-01-07 13:41:36 -08:00
Andrew Waterman
4608660f6e torture revealed a couple bugs 
FP loads/stores with certain negative offsets could cause illegal rounding
mode traps, and x's were cropping up in situations that are benign in HW.
 2012-12-04 05:57:53 -08:00
Andrew Waterman
cc067026a2 pipeline D$ response -> FPU regfile 2012-11-17 06:48:11 -08:00
Andrew Waterman
8dce89703a new D$ with better QoR and AMO pipelining 
Vector unit is disabled because nack handling needs to be fixed.
 2012-11-16 02:39:33 -08:00
Andrew Waterman
4d1ca8ba3a remove more global consts; refactor DTLBs 
D$ now contains DTLB. provide full VAddr with initial request.
VU now has its own DTLBs.
 2012-11-06 08:13:44 -08:00
Andrew Waterman
7380c9fe60 aggressively clock gate int and fp datapaths 2012-11-04 16:40:14 -08:00
Huy Vo
fd95159837 INPUT/OUTPUT orderring swapped 2012-07-12 18:16:57 -07:00
Andrew Waterman
f645fb4dd7 add L2$ 
It still has performance bugs but no correctness bugs AFAIK.
 2012-07-10 05:23:29 -07:00
Andrew Waterman
5035374f36 update to new chisel 2012-07-08 17:59:41 -07:00
Andrew Waterman
4e5f874266 update to new chisel/hwacha 2012-06-08 00:13:14 -07:00
Andrew Waterman
7f6319047e update to new scala/chisel/Mem 2012-06-06 02:47:22 -07:00
Huy Vo
7408c9ab69 removing wires 2012-05-24 10:42:39 -07:00
Andrew Waterman
65ff397122 improved instruction decoding 
it now makes use of don't-cares by performing logic minimization
 2012-05-01 20:16:36 -07:00
Andrew Waterman
5819beed64 use parameterized FP units 2012-05-01 01:25:43 -07:00
Andrew Waterman
7f254d9670 refine FP bugfixes 2012-04-01 14:52:33 -07:00
Huy Vo
c7c35322c2 two bug fixes to fpu 2012-03-31 22:23:51 -07:00
Andrew Waterman
7eb73c325e fix signedness of zero fmul results 
We were using the FMA unit to compute rs1 * rs2 + 0.0 for fmul,
which incorrectly computes +0.0 when rs1 * rs2 == -0.0.  Now we
add -0.0 if rs1*rs2 is negative.
 2012-03-10 00:21:51 -08:00