riscv/rocket-chip
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180 Commits

Author SHA1 Message Date
Andrew Waterman
e85c54cc4b New privileged ISA implementation 2015-03-14 02:49:07 -07:00
Christopher Celio
06dea3790a Removed sret from ptw; sret now comes thru io.cpu to dcache 2015-03-03 16:50:41 -08:00
Stephen Twigg
3d35ccd401 Explicitely convert results of Bits Muxes to UInt 
Chisel updated to emit SInt result instead of UInt so this commit addresses this change.
 2015-02-03 18:10:54 -08:00
Henry Cook
741e6b77ad Rename some params, use refactored TileLink 2015-02-01 20:37:31 -08:00
Andrew Waterman
b70f7683d3 Merge branch 'master' into ss-frontend 
Conflicts:
	src/main/scala/ctrl.scala
 2015-01-04 19:59:18 -08:00
Andrew Waterman
94b75c7cb1 Continue refactoring control 2015-01-04 15:32:05 -08:00
Andrew Waterman
6181de4cc9 Much refactor, so control 2015-01-03 13:34:38 -08:00
Christopher Celio
6749f67b7f Fixed BHT update error. 
- separated out BTB/BHT update
   - BHT updates counters on every branch
   - BTB update only on mispredicted and taken branches
 2014-11-16 22:02:27 -08:00
Christopher Celio
fea31d2167 Significant changes and fixes to BTB for superscalar fetch. 
- BTBUpdate only occurs on mispredicts now.
   - RASUpdate broken out from BTBUpdate (allows RASUpdate to be performed in
      Decode).
   - Added optional 2nd CAM port to BTB for updates (for when updates to the
      BTB may occur out-of-order).
   - Fixed resp.mask bit logic.
 2014-11-11 03:34:05 -08:00
Christopher Celio
99614e37aa Merge remote-tracking branch 'origin/master' into ss-frontend 
Conflicts:
	src/main/scala/btb.scala
	src/main/scala/core.scala
 2014-10-03 04:22:58 -07:00
Christopher Celio
180d3d365d Expanded front-end to support superscalar fetch. 2014-09-17 14:24:03 -07:00
Yunsup Lee
8abf62fae3 add LICENSE 2014-09-12 18:06:41 -07:00
Andrew Waterman
a999c055ed Don't take an interrupt when EX stage PC is invalid 
It was possible to take an interrupt on the instruction in the shadow of
a short forward branch.  EPC would thus get the wrong value, and so
a wrong-path instruction would be executed upon return from interrupt.

h/t Yunsup
 2014-09-11 01:46:52 -07:00
Henry Cook
b42a2ab40a Final parameter refactor 2014-09-01 13:28:58 -07:00
Henry Cook
0dac9a7467 Full conversion to params. Compiles but does not elaborate. 2014-08-19 11:38:02 -07:00
Henry Cook
910b3b203a removed AddressSpaceConstants, CacheConstants, and TileLinkSizeConstants 2014-04-10 12:32:44 -07:00
Andrew Waterman
f235fa0db6 Move branch resolution to M stage 2014-04-07 15:58:49 -07:00
Andrew Waterman
db59fc65ab Add return address stack 2014-04-01 15:01:27 -07:00
Yunsup Lee
ac4b3f9f22 print out core id 2014-03-04 23:38:49 -08:00
Yunsup Lee
98b830201a add wen signal to dasm printf 2014-02-25 03:31:06 -08:00
Yunsup Lee
97b1841fcf change dcache tag bits to 7 2014-02-22 22:53:04 -08:00
Andrew Waterman
a09ff9fdc7 Revert to old AUIPC definition 2014-02-10 19:04:42 -08:00
Quan Nguyen
f021213b1d Merge remote-tracking branch 'origin/master' into hwacha-port 2014-02-06 00:21:28 -08:00
Andrew Waterman
62e9313aef Add 16 microarchitectural counters 2014-02-06 00:13:02 -08:00
Yunsup Lee
ff7cae29f7 hookup rocc interrupt and s bit 2014-02-06 00:09:42 -08:00
Andrew Waterman
a7489920ce Support CSR atomics on all CSRs, not just STATUS 2014-01-21 16:17:39 -08:00
Andrew Waterman
e8486817e6 Clean up formatting (i.e. remove tabs, semicolons) 2014-01-13 21:43:56 -08:00
Andrew Waterman
4d236979bd Fix very far forward JALs 
We were sign-extending from the wrong bit, causing a backwards jump.
 2014-01-13 00:55:48 -08:00
Andrew Waterman
da3135ac9b Begin integer unit clean-up 
...to make it easier to generate the superscalar version of the core.
 2013-12-09 15:06:13 -08:00
Andrew Waterman
924261e2b2 Update to new privileged ISA... phew 2013-11-25 04:35:15 -08:00
Andrew Waterman
65b8340cea Mitigate D$ hit -> branch -> NPC critical path 2013-11-24 14:21:03 -08:00
Yunsup Lee
c1966e2b0a forgot to put htif into uncore package 2013-11-07 15:42:03 -08:00
Andrew Waterman
b44dafbdca Simplify branch offset mux 2013-10-29 13:20:40 -07:00
Andrew Waterman
1d2f4f8437 New ISA encoding, AUIPC semantics 2013-09-21 06:32:40 -07:00
Andrew Waterman
88d1c47665 don't disassemble within chisel 2013-09-15 04:14:45 -07:00
Andrew Waterman
f12bbc1e43 working RoCC AccumulatorExample 2013-09-14 22:34:53 -07:00
Andrew Waterman
18968dfbc7 Move store data generation into cache 2013-09-14 16:15:07 -07:00
Andrew Waterman
a0cb711451 Start adding RoCC 2013-09-14 15:31:50 -07:00
Andrew Waterman
d053bdc89f Remove Hwacha from Rocket 
Soon it will use the coprocessor interface.
 2013-09-12 22:34:38 -07:00
Andrew Waterman
243c4ae342 sync up rocket with new isa 2013-09-12 03:44:38 -07:00
Andrew Waterman
67f80ba4b2 Stall div/mul writeback until WB slot is free 2013-08-24 14:44:17 -07:00
Andrew Waterman
52e31f3298 Bypass scoreboard updates 
This reduces div/mul/D$ miss latency by 1 cycle.
 2013-08-24 14:44:04 -07:00
Andrew Waterman
d4a0db4575 Reflect ISA changes 2013-08-24 14:43:55 -07:00
Henry Cook
3a266cbbfa final Reg changes 2013-08-15 15:28:15 -07:00
Henry Cook
1a9e43aa11 initial attempt at upgrade 2013-08-12 10:39:11 -07:00
Henry Cook
4eaab214d2 Fold uncore constants into TileLinkConfiguration, update coherence API 2013-08-02 16:29:51 -07:00
Henry Cook
9abdf4e154 Make compatible with scala 2.10. List.sort deprecated. Refactor constants into package object. 2013-07-23 20:27:58 -07:00
Andrew Waterman
95c5147dc5 Add RISC-V instruction disassembler 2013-06-13 10:31:04 -07:00
Andrew Waterman
50ccc20bf3 replace RDNPC with AUIPC 2013-04-22 04:20:15 -07:00
Andrew Waterman
8cbdeb2abf add LR/SC support 2013-04-04 17:07:09 -07:00