50a283d311
move store data generation into EX stage
...
doing so removes it from the critical path of FP store unrecoding.
2012-02-12 01:35:55 -08:00
725190d0ee
update to new chisel
2012-02-11 17:20:33 -08:00
f8b937d590
fix 32-bit divider bug
...
thanks, torture!
also, tidied up the code a bit.
2012-02-09 03:47:59 -08:00
f47d888feb
vvcfgivl and vsetvl works
2012-02-09 02:35:21 -08:00
92493ad153
fix mul/div kill bug
...
occasionally, an in-progress multiply or divide could be
erroneously killed, tying up the register forever.
2012-02-09 02:26:03 -08:00
128ec567ed
make BTB fully associative; don't use it for JALR
...
JALR created a long path from the ALU in execute stage
to an address comparator to the next-PC mux. the benfit
was close to nil, anyway.
2012-02-09 01:34:00 -08:00
fcc8081c4d
hook up the vector command queue
2012-02-09 01:28:16 -08:00
8b6b0f5367
add external memory request interface for vec unit
2012-02-08 22:30:45 -08:00
9285a52f25
initial vu integration
2012-02-08 21:43:45 -08:00
b3f6f9a5fd
fix BTB misprediction check for negative addresses
...
also index BTB with PC, not PC+4
2012-02-08 15:05:28 -08:00
e9da2cf66a
improve id/ex datapath
...
move operand selection into decode stage; simplify bypassing
2012-02-08 06:47:26 -08:00
d471a8b2da
arbitrate for LLFU writebacks in MEM stage
2012-02-08 04:21:05 -08:00
5403d069e9
add fp loads/stores
2012-02-07 23:54:25 -08:00
fde8e3b696
clean up bypassing/hazard checking a bit
2012-02-06 17:26:45 -08:00
99a959e6b1
remove pc+4 piperegs and add new ex pc+4 adder
2012-02-02 13:33:27 -08:00
b1bbf56b74
clean up wb->id bypass
2012-02-01 16:41:18 -08:00
f1c355e3cd
check pc/effective address sign extension
2012-01-24 00:15:17 -08:00
8766438bb9
Updated chisel removes ^^ from language. Removed from rocket source, updated jar.
2012-01-23 17:09:23 -08:00
1d76255dc1
new chisel version jar and find and replace INPUT and OUTPUT
2012-01-18 14:39:57 -08:00
0369b05deb
move replays to writeback stage
2012-01-17 21:12:31 -08:00
bcb55e581a
remove host.start signal, use reset instead
2012-01-11 17:49:32 -08:00
20aee36c96
move PCR writes to WB stage
2012-01-02 15:42:39 -08:00
3045b33460
remove second RF write port
...
load miss writebacks are treated like mul/div now.
2012-01-02 02:51:30 -08:00
ffe23a1ee8
fix WAW hazard handling
2012-01-02 00:25:11 -08:00
eb657dd250
reduce superfluous replays
...
we only replay after a cache miss if we mis-scheduled the use of a load.
2012-01-01 21:28:38 -08:00
efc623cc36
validate BTB address and use BTB for J/JAL/JR/JALR
...
even if we weren't using the BTB for JR/JALR, we'd need to
flush the BTB on FENCE.I and on context switches, but
validating its result suffices instead.
2012-01-01 17:04:14 -08:00
2f8fcebea0
remove datapath register resets resets
2012-01-01 16:09:40 -08:00
733fc8e65e
booth multiplier
2011-12-20 03:49:07 -08:00
b5a8b6dc73
fix divider for RV32
2011-12-19 16:57:53 -08:00
bcceb08373
add dummy mul_rdy signal
2011-12-17 07:30:47 -08:00
82700cad72
fix multiplier for rv32
2011-12-17 07:20:00 -08:00
56c4f44c2a
hellacache returns!
...
but AMOs are unimplemented.
2011-12-12 06:49:39 -08:00
ce201559f3
Support cache->cpu nacks one cycle after request
2011-12-10 00:42:09 -08:00
c01e1f1cef
Don't replay from EX stage.
...
EX replays are now handled from MEM. We may move them to WB.
2011-12-09 19:42:58 -08:00
e70b41241c
changed branch addr generation to get it off critical path
2011-12-02 01:56:17 -08:00
da2fdf4f85
fixed console i/o
2011-11-30 22:51:59 -08:00
bc44572d99
bugfixes due to new hcl jar file
2011-11-30 21:54:55 -08:00
11f0e3daf4
more cleanup
2011-11-18 00:17:30 -08:00
c42d8149b7
moved PCR writeback to end of MEM stage, cleanup of dcache/dpath/ctrl
2011-11-17 23:50:45 -08:00
80b4253318
fixed dcache amo bug, cleaned up testharness, added RDTIME instruction
2011-11-16 02:04:28 -08:00
886857fa47
writes of PC weren't being sign extended
2011-11-15 18:07:36 -08:00
48cec01710
updated riscv-bmarks and riscv-tests to build with new toolchain
2011-11-15 00:11:22 -08:00
cd6e463320
added ei and di instructions
2011-11-14 13:48:49 -08:00
b791010bb1
flush.i invalidates I$ & ITLB, writing PTBR invalidates both TLBs
2011-11-14 04:13:13 -08:00
890bfa7c48
added IPIs and timer interrupts
2011-11-14 03:24:02 -08:00
5b29765917
synced up with supervisor mode state in latest ISA simulator
2011-11-14 01:37:20 -08:00
44419511b7
timer interrupt fixes
2011-11-13 00:32:08 -08:00
f86d5b1334
cleanup, lots of minor fixes, added more PCR regs (COREID, NUMCORES), parameterized BTB
2011-11-10 11:26:13 -08:00
4bd0263a4a
added misaligned instruction check, cleaned up badvaddr handling
2011-11-10 03:38:59 -08:00
603ede8bfe
access faults now write badvaddr PCR register with faulting address
2011-11-10 02:46:09 -08:00
Andrew Waterman
Yunsup Lee
Henry Cook
Andrew Waterman
Rimas Avizienis