riscv/rocket-chip
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Author SHA1 Message Date
Andrew Waterman 5a5b78b15e Improve L2 TLB coding style 2017-07-26 02:22:43 -07:00
Andrew Waterman 5a9c673f41 Fix L2 TLB response bug 
Sometimes, it would inform the L1 TLB that the translation was for
a superpage, even though that's never the case.
 2017-07-26 02:20:41 -07:00
Andrew Waterman acca0fccf5 Fix BTB not being refilled on some indirect jumps 
We are overloading the BTB-hit signal to mean that any part of the frontend
changed the control-flow, not just the BTB.  That's the right thing to do for
most of the control logic, but it means the BTB sometimes won't get refilled
when we'd like it to.  This commit makes the frontend use an invalid BTB entry
number when it, rather than the BTB, changes the control flow.  Since the
entry number is invalid, the BTB will treat it as a miss and refill itself.

This is kind of a hack, but a more palatable fix requires reworking the RVC
IBuf, which I don't have time for right now.
 2017-07-26 02:13:43 -07:00
Andrew Waterman 15878d4691 Perform some control-flow transfers within the Frontend 2017-07-25 15:19:16 -07:00
Andrew Waterman 62c4080585 Add RVC instruction patterns 2017-07-25 15:19:16 -07:00
Andrew Waterman 66d06460fa Add option for acquire-before-release 2017-07-25 15:19:16 -07:00
Andrew Waterman 86ccd935fc Add method to print perf events 2017-07-25 15:19:16 -07:00
Andrew Waterman 5df8f0d1ea Add L2 TLB miss counter 2017-07-25 15:19:16 -07:00
Andrew Waterman 3ced04b70a Mix in trait to connect global_reset_vector 2017-07-25 15:19:16 -07:00
Andrew Waterman b2351c5fbf Use consistent casing 2017-07-06 11:16:56 -07:00
Andrew Waterman be4eceec0d Fix stupid D$ probe bug 2017-07-06 01:20:47 -07:00
Andrew Waterman 90a7d6a343 Add L2 TLB option 2017-07-06 01:19:18 -07:00
Andrew Waterman 438abc76d2 Handle TL errors in L1 I$ 
Cache the error bit in the tag array; report precisely on access.
 2017-07-06 01:02:11 -07:00
Andrew Waterman 0ef45fac9b Add tag ECC to D$ 2017-07-03 18:16:37 -07:00
Andrew Waterman e9752f76ae Improve probe state machine 
- Reduce reliance on s2_prb_ack_data due to future ECC changes
- Shave a cycle off valid, but clean, probes
- Code cleanup
 2017-07-03 16:25:04 -07:00
Andrew Waterman b9a934ae28 Support eccBytes > 1 2017-06-28 02:09:18 -07:00
Andrew Waterman 8e4be40efc Propagate wb_reg_rs2 for sfence ASID 
This would have been a bug if we supported ASIDs.
 2017-06-28 02:09:18 -07:00
Andrew Waterman 2077e4190b Make log more sensible for long-latency operations 
Show only one write to the destination register, not two.
 2017-06-28 02:09:18 -07:00
Andrew Waterman 6f8fdff762 Basic L1 D$ ECC support 
Only supports ECC on data, not tags; only supports byte granularity.
 2017-06-28 02:09:18 -07:00
Andrew Waterman 6100600179 Minor D$ code cleanup 2017-06-28 02:09:18 -07:00
Andrew Waterman 9c78ac4d78 Add grouped method to AugmentedUInt, like Seq.grouped 2017-06-28 02:09:18 -07:00
Andrew Waterman 8989f5654c Add swizzle method to Encoding 2017-06-28 02:09:18 -07:00
Andrew Waterman 3e04a99f61 Refactor frontend exception passing 
Bundle them, and leverage regularity, so that if we have to add more
exceptions in the future, we don't need to change so much code.
 2017-06-28 02:09:18 -07:00
Andrew Waterman cc2f87c214 Forbid S-mode execution from user memory 
https://github.com/riscv/riscv-isa-manual/commit/285c81746fe664060b62ae0584865dbfa9f42e1a
 2017-06-28 02:09:18 -07:00
Andrew Waterman 8aa16a11f3 Reduce D$ access energy when refill width > access width 2017-06-28 02:09:18 -07:00
Andrew Waterman 25f585f2a9 Remove unused signal from TLB interface 2017-06-28 02:09:18 -07:00
Andrew Waterman d5f80df0ae Allow speculative I$ refill to cacheable regions 
Backpedaling on 27b143013f.  Shaving
four cycles off of I$ miss penalty is obviously worth the HW cost.
 2017-06-28 02:09:18 -07:00
Andrew Waterman a6d9884cc0 Improve integer mul/div 
- Signed integer multiplication latency is now deterministic (before,
it would take an extra cycle if the multiplier was negative).
- High-part multiplication is now one cycle faster.
- RV64 MULW now takes half as many cycles as MUL.
- Positive remainders are now one cycle faster.
 2017-06-19 12:09:21 -07:00
Andrew Waterman 76af15a6ff Fix FPU control bug for div/sqrt 
I was examining a WB-stage control signal instead of a MEM-stage control
signal.  I refactored the code to group the signals together, so that this
sort of bug is less likely going forward.
 2017-06-09 15:51:06 -07:00
Andrew Waterman 8552c77972 Fix I$ reset regression FU-357 
Can't rely on s2 TLB response, so mask using s2_valid.
 2017-06-09 00:48:24 -07:00
Andrew Waterman 07ad9203ff Fix FMUL sign of zero 2017-06-05 17:35:42 -07:00
Andrew WatermanandWesley W. Terpstra 16ecbdd5b2 Reduce fanout on critical I$ miss signal 2017-06-02 20:45:50 -07:00
Andrew WatermanandWesley W. Terpstra 27b143013f Improve ITLB QoR 
- No need to check cacheability
- Remove a gate delay from PMP path
 2017-06-02 20:45:50 -07:00
Andrew WatermanandWesley W. Terpstra 0ffb2c8baf Simplify and improve QoR of ShiftQueue 2017-06-02 20:44:52 -07:00
Andrew WatermanandWesley W. Terpstra 8229bdee03 Remove FP unboxing from FMA critical path 2017-06-02 20:44:52 -07:00
Andrew WatermanandWesley W. Terpstra 7504b47bbe Improve code quality in FP->FP and Int->FP units 2017-06-02 20:44:52 -07:00
Andrew WatermanandWesley W. Terpstra 84c4ae775f Improve QoR for FP->Int conversions 2017-06-02 20:44:52 -07:00
Andrew WatermanandWesley W. Terpstra 07968df183 Refactor FP Classify 2017-06-02 20:44:52 -07:00
Andrew WatermanandWesley W. Terpstra 6ecd58a977 Incorporate new div/sqrt unit 2017-06-02 20:44:15 -07:00
Andrew Waterman 7eefc12705 Support vectored stvec interrupts, too 
https://github.com/riscv/riscv-isa-manual/commit/137812654e54e5d765e21909679a2a24a38be123
 2017-05-07 15:40:08 -07:00
Andrew WatermanandAndrew Waterman c6135a02df Revert "rocket: hard-wire UXL/SXL fields to 0" 
This reverts commit ea0714bfcb.

We've waffled on this matter in the priv spec: https://github.com/riscv/riscv-isa-manual/commit/326bec83de23f4d2daf24cfed6b5251748cad632
 2017-05-07 15:23:21 -07:00
Andrew WatermanandAndrew Waterman dd1546fd69 Check PPN LSBs for superpage PTEs 
https://github.com/riscv/riscv-isa-manual/commit/5a32fe87820f2f0f7ffab16a4a33906e78e26abb
 2017-05-05 15:30:09 -07:00
Andrew WatermanandYunsup Lee 398600d4da Interlock to prevent ITIM hazard when tl.a.valid & tl.d.valid & !tl.d.ready 2017-05-04 00:57:29 -07:00
Andrew Waterman fa6ecdf813 Fix RVC/uncacheable instruction memory performance bug 
9c1d126965 was an incomplete fix, so
sometimes we were requesting pipeline replays when they weren't
necessary.
 2017-05-03 17:52:06 -07:00
Andrew Waterman 3a1a37d41b Support PutPartial in ScratchpadSlavePort 2017-05-02 03:07:02 -07:00
Andrew Waterman 938b089543 Remove legacy devices that use AMOALU 
I'm going to change the AMOALU API, and so I'm removing dependent dead code.
 2017-05-02 03:05:41 -07:00
Andrew Waterman f8151ce786 Remove subword load muxing in ScratchpadSlavePort 2017-05-02 00:14:46 -07:00
Andrew Waterman 044b6ed3f9 Improve logical ops in AMOALU 
As with integer ALU, shave off some muxing.
 2017-05-02 00:14:46 -07:00
Andrew Waterman f49172b5bc ScratchpadSlavePort doesn't support byte/halfword atomics 2017-05-02 00:14:46 -07:00
Andrew WatermanandAndrew Waterman dd85d7e0a0 I$: Don't raise io.resp.valid if io.s1_kill was high previous cycle 
@solomatnikov found the bug.  It doesn't manifest in Rocket because the
Frontend masks io.resp.valid with s2_valid.
 2017-04-28 16:44:58 -07:00
Andrew Waterman 7416f2a17e Unbreak groundtest 2017-04-28 02:10:33 -07:00
Andrew Waterman 8fd5ecdff8 Set io.cpu.resp.bits.addr for MMIO loads without affecting QoR 2017-04-27 19:50:38 -07:00
Andrew Waterman 7c70aa593e Minor stylistic and QoR improvements to PLIC 2017-04-27 19:35:20 -07:00
Andrew Waterman 99de42d34c Swap order of ITIM WidthWidget and Fragmenter 
e99fa057ac accidentally reversed them
 2017-04-27 15:30:02 -07:00
Andrew Waterman 8c10caeef9 Express PMP mask generation with incrementer, not adder 
DC apparently doesn't always pick up the ((x + 1) ^ x) idiom.
Use (x + ~(x + 1)) instead.
 2017-04-27 15:16:29 -07:00
Andrew Waterman b2b4725522 Fix zero-width wire issues when ITIM is disabled 2017-04-26 22:43:00 -07:00
Andrew Waterman e23ee274f6 Size hartid field with NTiles, not XLen 2017-04-26 20:11:43 -07:00
Andrew Waterman dc753bfa95 Fix I$ elaboration when ITIM is disabled 2017-04-26 19:35:35 -07:00
Andrew Waterman 80d826b94a Make DTIM deduplicatable 2017-04-26 19:35:35 -07:00
Andrew Waterman 418879a47f Add Instruction Tightly Integrated Memory 2017-04-26 19:35:35 -07:00
Andrew Waterman ee6702e5e0 Support indexing 1-entry Seqs 
It's a zero-width wire special case.

Closes #706.
 2017-04-26 19:35:35 -07:00
Andrew Waterman 2e23d46631 Use val instead of def in ECC calculations 
This allows nicer-looking code to avoid generating lots of redundant nodes.
 2017-04-26 19:35:35 -07:00
Andrew WatermanandAndrew Waterman 65928dc6a0 Don't push RAS for "auipc ra, X; jalr ra, ra, Y" 2017-04-24 02:01:15 -07:00
Andrew WatermanandAndrew Waterman 36a7971975 Bypass scoreboard to reduce MMIO latency 2017-04-24 02:01:15 -07:00
Andrew WatermanandAndrew Waterman 845e6f7458 Filter out duplicate test suites 
I botched the refactoring in 5934c7b4b9
 2017-04-24 02:01:15 -07:00
Andrew WatermanandAndrew Waterman f2d4cb8152 Update RAS speculatively from fetch stage 2017-04-24 02:01:15 -07:00
Andrew WatermanandAndrew Waterman 3b2c15b648 Use tininess-after-rounding in FPU 2017-04-24 02:01:15 -07:00
Andrew WatermanandAndrew Waterman c36c171202 Use correct interrupt priority order 2017-04-24 02:01:15 -07:00
Andrew WatermanandAndrew Waterman bf861293d9 Add ShiftQueue; use it 2017-04-24 02:01:15 -07:00
Andrew WatermanandAndrew Waterman d24d8ff84b Don't stall the frontend, making it easier to add more features later 2017-04-24 02:01:15 -07:00
Andrew WatermanandAndrew Waterman 061a0adceb Fetch smaller parcels from the I$ 2017-04-24 02:01:15 -07:00
Andrew WatermanandAndrew Waterman 458d80cb18 For Verilator, rename +start to +dump-start to match VCS 2017-04-20 17:00:46 -07:00
Andrew WatermanandAndrew Waterman 2faf8ea239 Add +dump-start=N option to VCS 
Starts dumping waveform on cycle N.

Can control stop cycle with +max-cycles.
 2017-04-20 17:00:46 -07:00
Andrew WatermanandMegan Wachs 67404a665b When not using a cache, LR/SC isn't legal even on cacheable memory 2017-04-20 08:47:03 -07:00
Andrew WatermanandAndrew Waterman d82a0dc231 Mitigate D$ exception critical path, yet again 2017-04-18 00:47:58 -07:00
Andrew WatermanandAndrew Waterman c99ce7ce5d Only report D$ exceptions on not-nacked accesses 2017-04-18 00:47:58 -07:00
Andrew WatermanandAndrew Waterman 5934c7b4b9 Fix description of LR/SC test suites 2017-04-18 00:47:58 -07:00
Andrew WatermanandAndrew Waterman a956b78dd2 In TLBPermissions, merge across some region types 
We only care whether they have side effects or not.
 2017-04-18 00:47:58 -07:00
Andrew WatermanandAndrew Waterman 6de6f38894 Pipeline D$ exception response into s2 2017-04-18 00:47:58 -07:00
Andrew WatermanandAndrew Waterman 657f4d4e0c Permit early grant acks to broadcast hub 2017-04-18 00:47:58 -07:00
Andrew WatermanandAndrew Waterman cc9ec1d51a Send D$ grant acks early; accept release acks early 
We now need to block the B-channel for a few cycles after a grant to
allow the processor to get at least one request through, preventing
livelock.
 2017-04-18 00:47:58 -07:00
Andrew WatermanandAndrew Waterman 728569c717 Reduce access-exception generation critical path 2017-04-18 00:47:58 -07:00
Andrew WatermanandAndrew Waterman a59a3f15e4 Disable LR/SC tests for scratchpad configs 2017-04-18 00:47:58 -07:00
Andrew WatermanandAndrew Waterman c366007a0d Tighten PMAs for LR/SC and misaligned accesses 
- LR/SC on cacheable memory only (not even scratchpad)
- No misaligned accesses on regions with get/put-effects
 2017-04-18 00:47:58 -07:00
Andrew WatermanandAndrew Waterman 74a7838de0 In TLBPermissions, don't merge regions of different types 2017-04-18 00:47:58 -07:00
Andrew WatermanandAndrew Waterman 7871ec82c4 Guarantee probe forward progress during LR storm 2017-04-18 00:47:58 -07:00
Andrew WatermanandYunsup Lee debcbca7de Make PMP tolerant to PA size << VA size 2017-04-17 10:28:33 -07:00
Andrew WatermanandYunsup Lee a454edaaf7 Treat exceptions as steps for the purposes of single-stepping 2017-04-17 10:28:33 -07:00
Andrew WatermanandAndrew Waterman 34d45b4fb0 Fix whitespace error 2017-04-14 01:03:11 -07:00
Andrew WatermanandAndrew Waterman fdfcffb0b2 Catch bad physical address MSBs when VA size > PA size 2017-04-14 01:03:11 -07:00
Andrew WatermanandAndrew Waterman 6fbbccca3e Improve Seq indexing QoR 2017-04-14 01:03:11 -07:00
Andrew WatermanandAndrew Waterman d203c4c654 Check AMO operation legality in TLB 2017-04-14 01:03:11 -07:00
Andrew WatermanandAndrew Waterman b9e042d2bf Unconditionally write badaddr, possibly to zero 
https://github.com/riscv/riscv-isa-manual/commit/59d33f6b833d6499edfa825a204933098345d53d
 2017-04-12 13:35:02 -07:00
Andrew WatermanandAndrew Waterman 9a983c12a3 Implement new FP encoding proposal 
https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/_r7hBlzsEd8/cWPyJKMzCQAJ
 2017-04-10 22:38:25 -07:00
Andrew WatermanandAndrew Waterman 470c6711a7 Do some CSE by hand, per @terpstra 2017-04-10 22:38:25 -07:00
Andrew WatermanandAndrew Waterman a43bf2feae Add vectored interrupt support 
https://github.com/riscv/riscv-isa-manual/commit/4dcaa944ba40e074d25516a157fc37f7491b71cc

I also added a test, which does indeed pass, but I don't want to bump
riscv-tools for that alone:

https://github.com/riscv/riscv-tests/commit/ba6d88466a96ec3147b96a57f746a137085764f9
 2017-04-08 00:29:45 -07:00
Andrew WatermanandAndrew Waterman 5c458322b5 bump chisel for withReset bugfix 2017-04-05 21:46:55 -07:00
Andrew WatermanandAndrew Waterman c861c4925e Don't signal access exceptions on invalid PTEs 
The PPN should not be interpreted in this case.
 2017-04-05 21:46:55 -07:00
Andrew WatermanandAndrew Waterman 2e09253d26 Revive I$ parity option 
Pipeline the parity check into the second stage, so that the data
RAM access + parity check do not become the critical path.
 2017-04-05 21:46:55 -07:00
Andrew WatermanandAndrew Waterman 43917dd59f Get I$ s1_kill signal off the critical path 2017-04-05 21:46:55 -07:00