Yunsup Lee
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98c0ea9875
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push rocket, tests, and vt-libs
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2012-12-07 16:59:15 -08:00 |
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Andrew Waterman
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10a6a42a4a
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make vlsi use dram model by default
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2012-12-06 03:13:45 -08:00 |
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Andrew Waterman
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d911e635d6
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simplify c++ memory models; support +dramsim flag
works for both vlsi and emulator
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2012-12-04 07:04:26 -08:00 |
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Andrew Waterman
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5dfb388f03
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update to newest rocket
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2012-11-27 02:43:31 -08:00 |
|
Andrew Waterman
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ea7029484e
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update to latest rocket
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2012-11-26 20:57:12 -08:00 |
|
Andrew Waterman
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e12af07722
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update to newest rocket
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2012-11-25 04:40:46 -08:00 |
|
Andrew Waterman
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9372912a9c
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update to newest rocket
|
2012-11-20 05:42:44 -08:00 |
|
Andrew Waterman
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6d47d18c2b
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catch sigterm to gracefully exit (fixes vcd)
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2012-11-20 05:40:44 -08:00 |
|
Andrew Waterman
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7330deb13a
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print stack trace if elaboration fails
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2012-11-20 05:39:48 -08:00 |
|
Yunsup Lee
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4d73e6e38a
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revamp vector yet again with new D$
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2012-11-18 03:14:22 -08:00 |
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Andrew Waterman
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7bcf59a18f
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support continous compilation via "make test"
for c++ emulator only, for now
|
2012-11-17 19:58:18 -08:00 |
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Andrew Waterman
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b58214d7e3
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remove more global constants
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2012-11-17 17:25:43 -08:00 |
|
Andrew Waterman
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cf05b604b3
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upgrade to new rocket; improve vlsi makefiles
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2012-11-17 07:21:29 -08:00 |
|
Andrew Waterman
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672e904c86
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update to new rocket/uncore
|
2012-11-16 02:41:50 -08:00 |
|
Yunsup Lee
|
1a91637673
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refactored vector queue interface
|
2012-11-07 01:16:02 -08:00 |
|
Yunsup Lee
|
29d4c0b857
|
refactored tlb
|
2012-11-06 23:54:14 -08:00 |
|
Andrew Waterman
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e2afae011a
|
factor out global constants
|
2012-11-06 08:18:40 -08:00 |
|
Yunsup Lee
|
1305372ce7
|
refactor flush logic
|
2012-11-05 23:01:08 -08:00 |
|
Yunsup Lee
|
9844ba1c1d
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revamp the vector unit with the new frontend
HAVE_PVFB is still broken, we need to multi-thread the frontend
|
2012-11-05 01:44:02 -08:00 |
|
Yunsup Lee
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dd6ee2571d
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add vector vm tests
|
2012-11-04 19:29:56 -08:00 |
|
Andrew Waterman
|
0c372fc9ec
|
refactor I$ config into RocketConfiguration
|
2012-11-04 17:00:19 -08:00 |
|
Andrew Waterman
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4ed2d614a2
|
update to new rocket; retime fpu in dc-syn
|
2012-11-04 16:43:02 -08:00 |
|
Henry Cook
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538b23c223
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Initial version of using sbt tasks to elaborate chisel source and invoke backends' makefiles
|
2012-10-23 12:52:59 -07:00 |
|
Henry Cook
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17d2bd8926
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Initial version of sbt tasks (elaborate task with no parameters)
|
2012-10-23 12:52:00 -07:00 |
|
Yunsup Lee
|
3edc1f42aa
|
revamp the backup memory link in the vlsi backend
|
2012-10-23 03:31:34 -07:00 |
|
Andrew Waterman
|
367b5489d1
|
first crack at continuous compilation/testing flow
try it out: cd emulator; make test
|
2012-10-19 04:09:07 -07:00 |
|
Andrew Waterman
|
1ad928cfe2
|
directly integrate dramsim build
also, build it as a static library to simplify dependencies
|
2012-10-18 18:59:37 -07:00 |
|
Andrew Waterman
|
edf0eeed01
|
integrate updated rocket/uncore
|
2012-10-18 17:51:41 -07:00 |
|
Miquel Moreto
|
6d49dc51a0
|
Fixed emulator Makefile + extra info in the README file
|
2012-10-16 11:06:48 -07:00 |
|
Miquel Moreto
|
aa3dc422b4
|
Added first README file
|
2012-10-15 10:54:47 -07:00 |
|
Miquel Moreto
|
5d75ddc553
|
Added dramsim2 memory model to the emulator backend
|
2012-10-14 14:06:28 -07:00 |
|
Yunsup Lee
|
34da073077
|
fix tab
|
2012-10-11 12:09:49 -07:00 |
|
Huy Vo
|
f67f8829e3
|
new rocket + uncore tags, added uncore dependencies to Makefrag
|
2012-10-10 15:44:19 -07:00 |
|
Andrew Waterman
|
7fd4eb6afd
|
update uncore
|
2012-10-09 18:05:32 -07:00 |
|
Andrew Waterman
|
c3236e6ee6
|
add missing symlink and update uncore
|
2012-10-09 17:51:33 -07:00 |
|
Huy Vo
|
24a49350cc
|
reference chip design
|
2012-10-09 13:05:56 -07:00 |
|
Huy Vo
|
93a0182b96
|
everything to get emulator working
|
2012-10-01 19:30:11 -07:00 |
|
Huy Vo
|
8560ea6e40
|
rename hwacha -> riscv-hwacha, chisel, riscv-asm-tests-bmarks, and uncore tags
|
2012-10-01 19:12:18 -07:00 |
|
Huy Vo
|
084a0d31c3
|
initial commit, all the relevant submodules
|
2012-09-26 17:46:17 -07:00 |
|