riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
509 Commits 1 Branch 0 Tags
3c95afebc65b5560c1a75a2102c4ae672ecbbd73
Commit Graph
48 Commits
This Branch
This Branch
All Branches
Author SHA1 Message Date
Howard Mao 3c95afebc6 Shift set index for multi-bank configurations 
Prior to this commit, the L2 cache banks used the lower bits of the
block address as the set index. However, the lower bits are also used to
route addresses to different banks. As a result, in multi-bank
configurations, only a fraction of the sets in each bank could be
accessed. This commit fixes that problem by using the bits ahead of the
bank index as the set index, so that all sets in the cache can be
accessed.
 2015-11-20 23:24:57 -08:00
Howard Mao 55a85cc67a make sure wmask is passed for PutBlock in broadcast hub 2015-11-20 14:09:24 -08:00
Howard Mao 941b64cd62 make partial write-masking PutBlock constructor always set alloc bit 2015-11-20 13:34:07 -08:00
Howard Mao 24f7b9f472 make sure L2MetadataArray assigns unoccupied way if available 2015-11-19 10:45:54 -08:00
Howard Mao e50c7ad306 add NASTI error assertions back in 2015-11-18 17:05:54 -08:00
Howard Mao e12efab423 skip meta_write state if no meta write pending 2015-11-13 13:50:35 -08:00
Howard Mao 7e7d688a01 make sure L2 passes no-alloc acquires through to outer memory 2015-11-12 15:40:58 -08:00
Howard Mao b3865c370a make sure correct addr_beat is sent for Get response by narrower/converter 2015-11-12 15:40:38 -08:00
Howard Mao f397d61033 add alloc option to Put constructor 2015-11-12 11:39:59 -08:00
Howard Mao 7733fbe6a3 make sure no-alloc write still updates data array if there is a cache hit 2015-11-12 11:39:36 -08:00
Howard Mao b59ce5fed4 make sure L2 waits for outer grant before sending grant for write request 2015-11-10 16:06:14 -08:00
Howard Mao 42d3d09d7a add a ClientTileLinkEnqueuer to complement the TileLinkEnqueuer 2015-11-09 11:49:19 -08:00
Howard Mao 7942be4e01 make sure outerTL method is idempotent 2015-11-09 11:10:02 -08:00
Howard Mao baa2544651 Fix some more issues with narrower 2015-10-31 19:36:30 -07:00
Howard Mao 812c5bcc55 make sure narrower can handle sub-block level requests correctly 2015-10-31 15:58:36 -07:00
Howard Mao d4b8653002 fix too strict assertion in broadcast hub 2015-10-31 15:58:10 -07:00
Howard Mao c10870a87c make sure ID width requirement in TL -> NASTI converter is correct 2015-10-27 13:25:29 -07:00
Howard Mao 9fa4541916 get rid of unused full signal in ReorderQueue 2015-10-26 12:17:25 -07:00
Howard Mao 6403f27fbe fix bug in ReorderQueue breaking TileLink Unwrapper 2015-10-22 15:52:55 -07:00
Howard Mao 02d113b39f outerDataBits / innerDataBits should be per beat, not per block 2015-10-21 11:31:13 -07:00
Howard Mao baf95533a4 fix combinational loop in TileLink Unwrapper 2015-10-20 23:26:11 -07:00
Howard Mao ffe7df2fed make sure TL -> NASTI converter acquire ready not dependent on valid 2015-10-20 22:09:22 -07:00
Howard Mao 1c135c1628 fix ready-valid mixup in TileLink unwrapper 2015-10-20 21:07:42 -07:00
Howard Mao d12403e7dc fix up and simplify TL -> NASTI converter logic 2015-10-19 13:47:13 -07:00
Howard Mao 49667aa4b0 make sure broadcast acquire tracker doesn't try to send requests back-to-back 2015-10-14 18:56:13 -07:00
Howard Mao 1d362d6d3a make sure correct parameters are used for TileLink constructors 2015-10-14 17:58:54 -07:00
Howard Mao 47da284e56 TileLinkNarrower should do nothing if interfaces are the same width 2015-10-13 13:28:47 -07:00
Howard Mao 83df05cb6a add TileLink data narrower 2015-10-13 12:45:39 -07:00
Howard Mao 993ed86198 move ReorderQueue to utils.scala 2015-10-13 09:49:22 -07:00
Howard Mao 1e7f656527 get release block address from inner release 2015-09-28 15:02:51 -07:00
Howard Mao 308022210a use updated NASTI channel constructors 2015-09-25 12:07:27 -07:00
Howard Mao 8c4ac0f4f3 make sure CSR/SCR data width matches xLen 2015-09-25 12:07:03 -07:00
Howard Mao d1f2d40a90 replace remaining uses of Vec.fill 2015-09-24 17:50:09 -07:00
Howard Mao 3ff830e118 ReorderQueue uses Vec of Bools instead of Bits for roq_free 2015-09-24 17:43:53 -07:00
Howard Mao 83740dfaa5 Merge branch 'master' of github.com:ucb-bar/uncore 2015-09-24 17:10:09 -07:00
Howard Mao 3b86790c3f replace NASTIMasterIO and NASTISlaveIO with NASTIIO 2015-09-24 16:58:20 -07:00
Howard Mao b4d21148ec get rid of NASTI error assertion 2015-09-22 09:43:42 -07:00
Howard Mao 8b2341b1b1 use reorder queue instead of extra tag bit to determine TL g_type in NASTI -> TL converter 2015-09-18 09:41:37 -07:00
Howard Mao bd536d8832 make HTIFModuleIO an anonymous bundle 2015-09-14 12:58:44 -07:00
Howard Mao 9d89d2a558 get rid of MemIO -> TileLink converters 2015-09-14 12:58:44 -07:00
Howard Mao f9965648f2 fix up some things in tilelink.scala 2015-09-14 12:57:54 -07:00
Howard Mao 64717706a9 get rid of non-NASTI RTC module 2015-09-14 12:57:54 -07:00
Howard Mao 6ee6ea4f1e use Put/Get/PutBlock/GetBlock constructors in broadcast hub 2015-09-14 12:57:54 -07:00
Howard Mao ae3d96013a make TL -> NASTI converter ingest ClientUncachedTileLinkIO and move functionality to Unwrapper 2015-09-14 12:57:54 -07:00
Howard Mao 21f96f382c split off SCR functionality from HTIF 2015-09-14 12:57:54 -07:00
Howard Mao bdc6972a8d separate RTC updates from HTIF 2015-09-14 12:56:44 -07:00
Howard Mao 24f3fac90a fix broadcast hub and TL -> NASTI converter to support subblock operations 2015-09-14 12:56:44 -07:00
Howard Mao a551a12d70 add missing Wire wrap in BasicCrossbar 2015-08-05 17:05:31 -07:00