Henry Cook
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38ae2707a3
|
refactor MemIO to not use params
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2015-10-06 11:41:48 -07:00 |
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Henry Cook
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3d10a89907
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refactor NASTI to not use param; new AddrMap class
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2015-10-06 11:41:47 -07:00 |
|
Howard Mao
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7b0167b92e
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make sure SCR and PCR data width matches xLen
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2015-09-25 12:13:22 -07:00 |
|
Howard Mao
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8d4d8680bf
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replace NASTIMasterIO and NASTISlaveIO with NASTIIO
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2015-09-24 16:59:13 -07:00 |
|
Howard Mao
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56ecdff52d
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Implement NASTI-based Mem/IO interconnect
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2015-09-22 10:32:31 -07:00 |
|
Andrew Waterman
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c6bcc832a1
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Chisel3: Don't use Vec.fill for IOs
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2015-09-20 13:43:56 -07:00 |
|
Andrew Waterman
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34b9a7fdc5
|
Various Chisel3 compatibility changes
|
2015-08-03 18:54:56 -07:00 |
|
Henry Cook
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51c42083d0
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Add new junctions repo as submodule (contains externally facing buses and peripherals).
Bump all submodules.
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2015-07-29 18:15:45 -07:00 |
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Henry Cook
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bd4ff35a4b
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Upgrade sbt to 0.13.8, simplify build.scala Tasks, generate tests from TestGenerator App, set addons with env variable ROCKETCHIP_ADDONS
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2015-07-22 11:49:10 -07:00 |
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Henry Cook
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302cd3e638
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Added BuildZscale param for use in Top and makefrag generation
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2015-07-13 15:46:42 -07:00 |
|
Henry Cook
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407d8e473e
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first cut at parameter-based testing
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2015-07-13 14:54:26 -07:00 |
|
Henry Cook
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d3ccec1044
|
Massive update containing several months of changes from the now-defunct private chip repo.
* Adds support for a L2 cache with directory bits for tracking L1 coherence (DefaultL2Config), and new metadata-based coherence API.
* Additional tests.
* New virtual memory implementation, priviliged architecture (1.7), custom CSRs, FDivSqrt unit
* Updated TileLink protocol, NASTI protocol SHIMs.
* Lays groundwork for multiple top-level memory channels, superscalar fetch.
* Bump all submodules.
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2015-07-02 14:43:30 -07:00 |
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Henry Cook
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0b5f23a209
|
Streamlined uncore for release
|
2014-10-06 13:37:15 -07:00 |
|
Adam Izraelevitz
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15fb4730ec
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Add BuildTile parameter for Tile
Conflicts:
rocket
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2014-09-25 06:50:45 -07:00 |
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Henry Cook
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5a840c5520
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support for multiple tilelink paramerterizations in same design
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2014-09-25 06:50:30 -07:00 |
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Yunsup Lee
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1cfd9f5a0e
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add LICENSE
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2014-09-12 10:15:04 -07:00 |
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Henry Cook
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82467313dd
|
merge in rocketchip changes from master
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2014-09-02 13:51:57 -07:00 |
|
Yunsup Lee
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7734285507
|
forgot to comment out hwacha
|
2014-09-01 09:01:36 -07:00 |
|
Yunsup Lee
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c03c09ec31
|
update for rocket-chip release
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2014-08-31 20:26:55 -07:00 |
|
Henry Cook
|
78ab83d224
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refactor fpga top/config
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2014-08-28 13:07:54 -07:00 |
|
Henry Cook
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bf356b9cb4
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Refactor to combine fpga and vlsi tops, part 1
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2014-08-24 19:30:53 -07:00 |
|
Henry Cook
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a41d55b643
|
Final parameter refactor.
|
2014-08-23 01:26:03 -07:00 |
|
Henry Cook
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1563c1bb36
|
Fixed cache params. Asm and bmark tests pass.
|
2014-08-12 15:00:54 -07:00 |
|
Henry Cook
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7f07771600
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Cache utility traits. Completely compiles, asm tests hang.
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2014-08-11 18:37:10 -07:00 |
|
Henry Cook
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1983260e6f
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a few more fixes. some param lookups fail (here() in Alter blocks)
|
2014-08-10 23:08:21 -07:00 |
|
Henry Cook
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63bd0b9d2a
|
Partial conversion to params. Compiles but does not elaborate. Rocket and uncore conversion complete. FPGA and VLSI config are identical. HwachaConfig and MemoryControllerConfig not yet removed.
|
2014-08-08 12:27:47 -07:00 |
|
Adam Izraelevitz
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08d81d0892
|
First cut at using new chisel parameters for toplevel parameters and fpu
|
2014-08-01 18:09:37 -07:00 |
|
Henry Cook
|
434da22283
|
Refactored Metadata, expanded coherence API (bump rocket, uncore, chisel)
|
2014-05-28 17:16:49 -07:00 |
|
Henry Cook
|
b0ccb88982
|
make outer cache type choice a top-level const
|
2014-05-28 14:46:07 -07:00 |
|
Henry Cook
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ce056b4b89
|
client/master -> inner/outer
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2014-04-29 16:50:30 -07:00 |
|
Henry Cook
|
224e286dd3
|
New uncore config objects. Backends get their own file. Simplify fpga uncore.
|
2014-04-26 19:46:11 -07:00 |
|
Henry Cook
|
3d4273954a
|
TileLinkIO.GrantAck -> TileLinkIO.Finish
|
2014-04-26 15:19:25 -07:00 |
|
Henry Cook
|
2cb4dbae39
|
Refactored uncore constants and tilelink data
|
2014-04-10 13:19:50 -07:00 |
|
Henry Cook
|
5a5f69bfca
|
finished uncore constant/tilelink data refactor
|
2014-04-10 13:13:46 -07:00 |
|
Andrew Waterman
|
817517c663
|
Better branch prediction
|
2014-04-07 16:08:06 -07:00 |
|
Henry Cook
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56f515c255
|
first steps in uncore constant/tilelink data refactor
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2014-03-30 09:21:08 -07:00 |
|
Andrew Waterman
|
d055c0ebaf
|
Push rocket/hardfloat/chisel
|
2014-03-04 16:39:06 -08:00 |
|
Yunsup Lee
|
e20d50436a
|
committed in the wrong directory, meant to commit in the hwacha directory
|
2014-03-01 00:01:35 -08:00 |
|
Yunsup Lee
|
8c459df3b6
|
flush deck when xcpt occurs, fixes remaining p test bugs
|
2014-02-28 22:50:34 -08:00 |
|
Stephen Twigg
|
755293d785
|
Push hwacha (refactoring) and add line that when uncommented properly instantiates hwacha).
|
2014-02-14 10:12:09 -08:00 |
|
Andrew Waterman
|
11e69a73cd
|
Fix tests when !hwacha; disable hwacha by default
|
2014-02-06 03:08:33 -08:00 |
|
Stephen Twigg
|
8c96e27ca6
|
Merge branch 'master' into hwacha-port
Mostly Stable version that is passing tests
|
2014-02-04 17:20:28 -08:00 |
|
Henry Cook
|
382fa0ef27
|
cleanups supporting uncore hierarchy
|
2014-01-31 16:03:58 -08:00 |
|
Stephen Twigg
|
e7ee94bcc8
|
Merge branch 'master' into hwacha-port
|
2014-01-21 15:23:05 -08:00 |
|
Stephen Twigg
|
ee0c4ca291
|
Push chisel, rocket, hwacha, tools, tests to incorporate a bunch of new changes (ISA alterations)
|
2014-01-21 14:48:04 -08:00 |
|
Andrew Waterman
|
6f028b2d52
|
Increase BTB size; fix Rocket FPU bug
|
2014-01-17 03:53:08 -08:00 |
|
Andrew Waterman
|
a43cf9d688
|
Update to new privileged ISA
|
2013-11-25 04:45:06 -08:00 |
|
Stephen Twigg
|
e50c5180cd
|
Merge branch 'master' into hwacha
|
2013-11-14 16:03:55 -08:00 |
|
Yunsup Lee
|
1d6d4b4e96
|
move htif to uncore
|
2013-11-07 13:19:19 -08:00 |
|
Yunsup Lee
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c810847761
|
hookup all memory ports
|
2013-11-05 17:12:25 -08:00 |
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