Howard Mao
04d92dddbd
add back decoupled NASTI connection at edge of RocketChip
2015-11-05 10:48:32 -08:00
Yunsup Lee
51116e0674
add 2 and 4 memory channel configs
2015-11-05 10:48:32 -08:00
Yunsup Lee
0d245741bc
add multichannel NASTI support in Verilog testbench
2015-11-05 10:48:32 -08:00
Howard Mao
9dabcab9c2
Get rid of MemIO in Top and replace with AXI throughout
2015-11-05 10:48:32 -08:00
Henry Cook
3698153535
OHToUInt instead of PriorityEncoder on Acq/RelMatches signals in L2Bank
2015-11-03 14:31:35 -08:00
Howard Mao
baa2544651
Fix some more issues with narrower
2015-10-31 19:36:30 -07:00
Howard Mao
812c5bcc55
make sure narrower can handle sub-block level requests correctly
2015-10-31 15:58:36 -07:00
Howard Mao
d4b8653002
fix too strict assertion in broadcast hub
2015-10-31 15:58:10 -07:00
Colin Schmidt
032bdd0601
Merge pull request #24 from ucb-bar/regression-master
...
Add a "--master" flag to the regression script
2015-10-29 14:15:44 -07:00
Palmer Dabbelt
3d2a4ffdd6
Add a "--master" flag to the regression script
...
I want to be able to test the master of riscv-gnu-toolchain against the current
RTL as part of the buildbot. This flag takes a list of repositories (by their
submodule path) and updates those to the current master, which facilitates that
check.
2015-10-29 14:11:26 -07:00
Howard Mao
c10870a87c
make sure ID width requirement in TL -> NASTI converter is correct
2015-10-27 13:25:29 -07:00
Colin Schmidt
86d67051b2
Merge commit 'e31be75' into rocc-fpu-port
2015-10-26 16:29:51 -07:00
Howard Mao
eb62ff6a50
add queues between Nasti -> TL converter and Nasti interconnect
2015-10-26 14:15:25 -07:00
Howard Mao
f37938e4de
implement MultiChannel routing
2015-10-26 14:15:25 -07:00
Howard Mao
9fa4541916
get rid of unused full signal in ReorderQueue
2015-10-26 12:17:25 -07:00
Yunsup Lee
a175afae73
make ZscaleChip work with new parameters framework
2015-10-25 10:24:39 -07:00
Yunsup Lee
c7235fecb5
further state optimization in CSRfile when not UseVM
2015-10-25 10:23:46 -07:00
Howard Mao
c3a7dcf0ab
fix missing cde library dependencies in submodules
2015-10-23 15:05:19 -07:00
Colin Schmidt
854feab08e
add knob and constraint dumping
2015-10-22 17:25:38 -07:00
Colin Schmidt
652fb393a3
Merge remote-tracking branch 'origin/master' into rocc-fpu-port
2015-10-22 16:38:28 -07:00
Howard Mao
6403f27fbe
fix bug in ReorderQueue breaking TileLink Unwrapper
2015-10-22 15:52:55 -07:00
Jim Lawson
0c587704a7
Add ability to generate libraryDependency on cde.
2015-10-22 11:37:20 -07:00
Jim Lawson
4c2b0a9032
Add ability to generate libraryDependency on cde.
2015-10-22 09:57:02 -07:00
Henry Cook
9769b2747c
now depend on external cde library rather than chisel.params (bump all submodules)
2015-10-21 18:24:16 -07:00
Henry Cook
47bc193c16
added CDE library as submodule
2015-10-21 18:24:16 -07:00
Henry Cook
4f8468b60f
depend on external cde library
2015-10-21 18:19:23 -07:00
Henry Cook
f8594da1d3
depend on external cde library
2015-10-21 18:17:17 -07:00
Colin Schmidt
942f6a7d7f
Merge commit 'd1eae61970f864afe4fde8ca7f75380c70c4658f' into rocc-fpu-port
2015-10-21 17:18:20 -07:00
Howard Mao
21f342ad42
fix typo causing L2 cache configuration to fail
2015-10-21 13:37:33 -07:00
Colin Schmidt
97f29b1618
Merge remote-tracking branch 'origin/master' into rocc-fpu-port
2015-10-21 11:33:42 -07:00
Howard Mao
02d113b39f
outerDataBits / innerDataBits should be per beat, not per block
2015-10-21 11:31:13 -07:00
Howard Mao
d5a75fd113
accidentally committed some code I didn't mean to in Rocket
2015-10-21 09:21:54 -07:00
Howard Mao
0b7c828b5d
go back to using standard LockingArbiter
2015-10-21 09:15:51 -07:00
Howard Mao
693a4ae00e
fix some more memory system bugs
2015-10-20 23:29:59 -07:00
Howard Mao
baf95533a4
fix combinational loop in TileLink Unwrapper
2015-10-20 23:26:11 -07:00
Howard Mao
c68d9f8137
make ProbeUnit state machine easier to understand
2015-10-20 23:25:23 -07:00
Howard Mao
ffe7df2fed
make sure TL -> NASTI converter acquire ready not dependent on valid
2015-10-20 22:09:22 -07:00
Howard Mao
c311c9938e
nitpicky declaration move
2015-10-20 21:10:54 -07:00
Howard Mao
1c135c1628
fix ready-valid mixup in TileLink unwrapper
2015-10-20 21:07:42 -07:00
Henry Cook
62765e9609
L2 rowBits param bugfix
2015-10-20 18:57:19 -07:00
Henry Cook
3fc630405b
Vectorize RoCC and Tile memory interfaces (bump uncore, rocket, zscale)
2015-10-20 15:05:12 -07:00
Henry Cook
1a1185be3f
Vectorize ROCC and Tile memory interfaces
2015-10-20 15:02:24 -07:00
Henry Cook
4389b9edb0
tilelink parameter tweak: addrBits now a constant
2015-10-20 15:00:30 -07:00
Howard Mao
4346111d2a
fix remaining vsim harness typo
2015-10-19 20:20:14 -07:00
Howard Mao
896aa892d1
bump uncore for TL -> NASTI converter fix
2015-10-19 15:31:59 -07:00
Howard Mao
d12403e7dc
fix up and simplify TL -> NASTI converter logic
2015-10-19 13:47:13 -07:00
Colin Schmidt
2cee8c8bec
Merge commit '3c3e35a56e954b35e6ceb17179ebadc52e8d9b3f' into rocc-fpu-port
2015-10-18 13:09:17 -07:00
Henry Cook
8c3370c2e3
L2 AMOALU bugfix and simpler TileLinkParameters (bump rocket, uncore, zscale)
2015-10-16 19:15:47 -07:00
Henry Cook
6f8997bee9
Minor refactor of StoreGen/AMOALU.
2015-10-16 19:12:46 -07:00
Henry Cook
1441590c3b
add enabled field to BTBParameters
2015-10-16 19:12:39 -07:00
