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Author SHA1 Message Date
Wesley W. Terpstra 36f4584bb1 axi4: Test AXI4-Lite in regression 2017-05-08 00:31:35 -07:00
Wesley W. Terpstra 3209e58845 axi4: SRAM support 0 userBits 2017-05-08 00:31:14 -07:00
Wesley W. Terpstra db76ff2d86 axi4: Deinterleaver must gather R also for single ID 
In order to guarantee that a complete R can be sent without
sinking B, the Deinterleaver must do its job even on AXI-Lite.
 2017-05-08 00:17:06 -07:00
Wesley W. Terpstra 8fc27b0bf2 axi4: IdIndexer; a single ID does NOT imply no response interleaving 
Some slaves may never send R until you process their B.
Thus, while there is no read response interleaving, there
is still interleaving between R and B, which breaks AXI4ToTL.
 2017-05-08 00:17:06 -07:00
Wesley W. Terpstra 4847c32599 tilelink: ToAXI4 - must interlock till last beat 
AXI4 makes no guarantee that bursts are handled atomicly.
Thus, you could be part-way through a read burst and suddenly
a write cuts ahead and is visible later, violating FIFO.
 2017-05-08 00:17:06 -07:00
Wesley W. Terpstra 8169ba6411 axi4: IdIndexer now handles 0-width IDs 2017-05-08 00:17:02 -07:00
Wesley W. Terpstra fe280187a1 axi4: Fragmenter cuts all input channel readys 
AXI4 forbids any input to lead combinationally to an output.For the AXI4ToTL
direction, front-load the cuts for {AW, AR, W}.readyAXI4ToTL makes the R and
B channels irrevocable.
 2017-05-01 22:53:41 -07:00
Wesley W. Terpstra 3d06f01a2c rocket: turn on early ack for ITIM 2017-05-01 22:53:41 -07:00
Wesley W. Terpstra 58a4529cc5 axi4: the last missing piece for safe FIFO ordering 2017-05-01 22:53:41 -07:00
Wesley W. Terpstra b0b5601e8d axi4: ToTL correct error handling 
If there is an illegal AWADDR = 0x2 on a 32-bit bus, remapping it
to an aligned address on the error device may make the mask
inconsistent with the address + size.
 2017-05-01 22:53:41 -07:00
Wesley W. Terpstra 661015a78d axi4: switch arbiter to round robin 2017-05-01 22:53:41 -07:00
Wesley W. Terpstra 976af7a8c7 tilelink2: better width inference for {left,right}OR 2017-05-01 22:53:41 -07:00
Wesley W. Terpstra 40f18e6e43 diplomacy: optimize IdRange overlap detection 2017-05-01 22:53:41 -07:00
Wesley W. Terpstra 30f1f1e7c7 rocket: turn on early ack for DTIM 2017-05-01 22:53:41 -07:00
Wesley W. Terpstra 6ee69454c3 tilelink2: Fragmenter now supports early Ack 2017-05-01 22:53:41 -07:00
Wesley W. Terpstra e09fa866b7 tilelink2: FIFOFixer should NOT change client request status 
Just because some clients are not FIFO does not matter. Downstream
FIFOFixers will still present a legitimate single domain to those
client who care.
 2017-05-01 22:53:41 -07:00
Wesley W. Terpstra a71f708dc7 rocketchip: move the Error device to 0x3000 2017-05-01 22:53:41 -07:00
Wesley W. Terpstra d27e1928dd axi4: make maxFlight a per-master parameter 2017-05-01 22:53:40 -07:00
Wesley W. Terpstra e1a072a644 axi4: massage test cases into shape again 2017-05-01 22:53:40 -07:00
Wesley W. Terpstra 9f08c484bd tilelink2: ToAXI4 provide FIFO order semantics 2017-05-01 22:53:40 -07:00
Wesley W. Terpstra 61a6f94196 axi4: get unit tests legal again 2017-05-01 22:53:40 -07:00
Wesley W. Terpstra bf5cb396b9 rocketchip: relax mmio no-interleaving requirement 2017-05-01 22:53:40 -07:00
Wesley W. Terpstra 24f577c156 axi4: Deinterleaver ensures R channel ID does not change till last 2017-05-01 22:53:40 -07:00
Wesley W. Terpstra b4188ee625 axi4: ToTL supporting pipelined MMIO 2017-05-01 22:53:40 -07:00
Wesley W. Terpstra ca2cb033cd rocketchip: fix uses of AXI4 Fragmenter 2017-05-01 22:53:40 -07:00
Wesley W. Terpstra e100a943ea axi4: simplify Fragmenter by using user bits 2017-05-01 22:53:40 -07:00
Wesley W. Terpstra 7a1d107c9e rocketchip: include an ErrorSlave by default 2017-05-01 22:53:37 -07:00
Wesley W. Terpstra 641a4d577a tilelink2: Error device for returning errors on demand 2017-05-01 22:53:02 -07:00
Wesley W. Terpstra a580b17ece axi4: IdIndexer => reduce number of needed ids 2017-05-01 22:53:01 -07:00
Wesley W. Terpstra 06efc01d96 axi4: an adapter to remove user bits 2017-05-01 22:53:01 -07:00
Wesley W. Terpstra f1217519f1 axi4: RegisterRouter; concurrent response illegal in AXI 2017-05-01 22:53:01 -07:00
Wesley W. Terpstra 5163ccd11f axi4: RegisterRouter supports user bits 2017-05-01 22:53:01 -07:00
Wesley W. Terpstra de6ea9b442 axi4: support user bits in SRAM 2017-05-01 22:53:01 -07:00
Wesley W. Terpstra 396ecacda4 AXI4: add an optional user bundle field 2017-05-01 22:53:01 -07:00
Wesley W. TerpstraandGitHub f3ab23d068 dcache: fix stupidly wrong crossing comparison (#703) 2017-04-25 09:18:41 -07:00
Wesley W. TerpstraandGitHub 4807ce7ced dcache: put a flow Q to absorb back-pressure without restarting pipeline (#701) 
* dcache: put a flow Q to absorb back-pressure without restarting pipeline

When used with a RationalCrossing, pipelined MMIO does not come out cleanly.
The first beat works, but if the second beat gets stalled, the pipeline is
restarted. This is a quick hacky test to absorb the beats. Perhaps a better
fix can be made to achieve the same effect.

* dcache: provision as few stages as possible
 2017-04-24 23:28:04 -07:00
Wesley W. TerpstraandGitHub 9c1d126965 Allow speculative fetch to uncacheable memory if it hits in I$ (#700) 
@aswaterman it's in
 2017-04-24 19:12:37 -07:00
Wesley W. TerpstraandGitHub 11ff4dfbb9 rocket: seip (int 9) is only present if VM is enabled (#699) 2017-04-24 15:58:33 -07:00
Wesley W. TerpstraandGitHub d0f3004097 tilelink2: help tools save some registers in the WidthWidget (#691) 2017-04-24 15:13:58 -07:00
Wesley W. TerpstraandGitHub b4d17c76d1 coreplex: make rational+synchronous crossing configurable (#688) 2017-04-19 16:16:05 -07:00
Wesley W. TerpstraandGitHub db5d0737f0 Merge pull request #682 from ucb-bar/jchang 
Add hooks to print debug information into the graphml file
 2017-04-14 19:35:17 -07:00
Wesley W. Terpstra 7b8af96fc2 diplomacy: use circles for nodes again 2017-04-14 18:09:14 -07:00
Wesley W. Terpstra 2f22fca615 rocket: reverse input edge for better output 2017-04-14 18:09:14 -07:00
Wesley W. Terpstra ae8fd0c60f graphML: don't draw unconnected LazyModules 2017-04-14 18:09:14 -07:00
Wesley W. Terpstra fcf774f125 graphML: reverse interrupt arrows 2017-04-14 18:09:14 -07:00
Wesley W. TerpstraandGitHub 153178ac4f Merge pull request #678 from ucb-bar/rammodel-atomics 
RAMModel atomics
 2017-04-14 18:08:33 -07:00
Wesley W. Terpstra ba8be17c9a tilelink2: RAMModel, use CRC16 to check AMO response 2017-04-14 15:13:40 -07:00
Wesley W. Terpstra 6aeec673f2 util: add a CRC calculator 2017-04-14 15:13:40 -07:00
Wesley W. Terpstra d794218ec3 tilelink2: RAMModel now checks atomic results 2017-04-14 15:13:40 -07:00
Wesley W. Terpstra 4f0ae1eab7 tilelink2: annotate which test generates RAMModel output 2017-04-14 15:13:40 -07:00
Wesley W. Terpstra 0b65fe9532 unittest: put AtomicAutomata under regression 2017-04-14 15:13:39 -07:00
Wesley W. Terpstra 248acbd1b4 tilelink2: add a generic TL2 atomic evaulation unit 2017-04-14 15:13:39 -07:00
Wesley W. TerpstraandGitHub 37c9ab3459 Merge pull request #671 from ucb-bar/cork-it 
Add a few diplomacy restrictions
 2017-04-11 15:55:37 -07:00
Wesley W. Terpstra 1c36ab8bf7 Fragmenter: forbid multiple sink IDs 
Otherwise a slave might respond with different IDs for different
requests and the Fragmenter would violate the requirement that
control signals remain unchanged for a burst.
 2017-04-11 12:38:00 -07:00
Wesley W. Terpstra 84dc2ae822 CacheCork: remove probe support 2017-04-11 12:34:18 -07:00
Wesley W. TerpstraandGitHub 71bf929505 maskgen: support wider granularity result (#665) 
Sometimes it is useful to generate a mask with bits that correspond
to a larger unit than bytes.
 2017-04-09 20:06:23 -07:00
Wesley W. TerpstraandAndrew Waterman 2f2b472098 rocket: split the interrupt controller into its own node 2017-03-30 00:36:23 -07:00
Wesley W. TerpstraandAndrew Waterman a2fc51d65e soc: compatible with "simple-bus" => scanned for platform devices 2017-03-30 00:36:23 -07:00
Wesley W. TerpstraandGitHub ed38787c36 Merge pull request #622 from ucb-bar/priv-1.10 
Various priv-1.10 changes
 2017-03-27 19:28:30 -07:00
Wesley W. Terpstra 5b339b6bbd tilelink2 Monitor: catch incorrect use of source ID 2017-03-27 16:30:46 -07:00
Wesley W. Terpstra 75eba294ec DCache: Release from the correct ID as well 2017-03-27 16:30:46 -07:00
Wesley W. Terpstra 4959771c97 Revert "For D$, use source 0 through N-1 for MMIO, not 1 through N" 
This reverts commit 0538dc77ce.
 2017-03-27 16:30:46 -07:00
Wesley W. Terpstra fa7ead6357 Revert "Use Reg(Vec) instead of Seq(Reg) for DCache MMIO" 
This reverts commit fb6498f2c3.
 2017-03-27 16:30:46 -07:00
Wesley W. TerpstraandGitHub 722b0d521f bootrom: also setup SBI a0+a1 for when we hang (#617) 
This way a program started by the debugger still has the DTB handy.
 2017-03-27 00:01:05 -07:00
Wesley W. TerpstraandGitHub 986e1754be Merge pull request #611 from ucb-bar/expose-back-side-bus 
rename l2FrontendBus as fsb, expose bsb
 2017-03-24 23:32:50 -07:00
Wesley W. Terpstra 537274b645 coreplex: move buffers inside the coreplex 
This should make hierarchical place and route easier.
 2017-03-24 22:54:48 -07:00
Wesley W. TerpstraandGitHub 19485a9861 Merge pull request #609 from ucb-bar/dtb-rom 
DTB in the bootrom
 2017-03-24 21:54:13 -07:00
Wesley W. Terpstra e74226564c travis: add dependency on device-tree-compiler 2017-03-24 20:59:33 -07:00
Wesley W. Terpstra f36b1766f8 TLROM: use the smallest ROM implementation that works 
The contents everywhere else are still zero.
 2017-03-24 20:40:28 -07:00
Wesley W. Terpstra ac205ca10a bootrom: move to 0x10000 for more space (DTB on multicore is big) 2017-03-24 18:18:01 -07:00
Wesley W. Terpstra 34f8ce653a bootrom: follow SBI (a0=hartid, a1=dtb) 2017-03-24 18:18:01 -07:00
Wesley W. Terpstra 9a2f0d01a1 GenerateBootROM: use compiled DTB 2017-03-24 18:18:01 -07:00
Wesley W. TerpstraandGitHub bd08f10816 tilelink2: make sink ids optional (#607) 
* tilelink2: make sink ids optional

* CacheCork: add a special-case for 1 sink id
 2017-03-23 18:19:04 -07:00
Wesley W. TerpstraandGitHub 19eb9b6906 l1tol2: put a flow Q on the exits (#606) 
This Xbar connects the largest components in the design; the cores
and the L2 banks. We already have a full buffer on the core side.
However, the valid path going to the L2 comes back as a ready path.
Putting a flow Q also on the outputs of the l1tol2 cuts this path
in half at no cost to IPC.
 2017-03-23 16:28:32 -07:00
Wesley W. TerpstraandGitHub 4f78eafbdf Merge pull request #602 from ucb-bar/tl-mmio-pipeline 
TL pipeline MMIO
 2017-03-21 14:59:11 -07:00
Wesley W. Terpstra 4c00066746 rocket: describe dcache as two clients (fifo+cached) 2017-03-21 11:16:51 -07:00
Wesley W. Terpstra 81d717e82f coreplex: guarantee FIFO for those tiles that need it 2017-03-21 11:16:51 -07:00
Wesley W. Terpstra 198afddb4b tilelink2: add the FIFOFixer 2017-03-21 11:16:51 -07:00
Wesley W. Terpstra c33f31dd3c tilelink2 RAMModel: weaken fifo requirement check 2017-03-21 11:16:51 -07:00
Wesley W. Terpstra 930438adba tilelink2 SourceShrinker: destroy FIFO behaviour 2017-03-21 11:16:51 -07:00
Wesley W. Terpstra fd521c56a6 tilelink2: add client-side FIFO parameterization 2017-03-21 11:16:51 -07:00
Wesley W. TerpstraandGitHub d4c9c13fb4 Merge pull request #600 from ucb-bar/monitor-spec 
Update monitor spec
 2017-03-20 15:23:34 -07:00
Wesley W. Terpstra 4eef317e84 RegisterRouter: support devices with gaps 2017-03-20 14:49:22 -07:00
Wesley W. Terpstra 431cb41e27 tilelink2 Parameters: clarify client minLatency is B=>C, not D=>E 2017-03-20 14:49:22 -07:00
Wesley W. Terpstra 04892fea01 Monitor: support early ack 2017-03-20 14:49:19 -07:00
Wesley W. Terpstra 278f6fea24 tilelink2: define is{Request,Response} based on spec 2017-03-20 13:41:02 -07:00
Wesley W. Terpstra 778e189bba Monitor: ProbeAckData and ReleaseData may carry an error 2017-03-20 11:44:13 -07:00
Wesley W. Terpstra 48c7aed4e1 Monitor: any probe supported by the client is legal 2017-03-20 11:34:19 -07:00
Wesley W. TerpstraandGitHub 5a50acfd9d Merge pull request #595 from ucb-bar/ignore-tl-c 
Ignore TL-C
 2017-03-19 18:49:11 -07:00
Wesley W. Terpstra 0c92283a61 rocket icache: tie off b ready 2017-03-19 17:18:50 -07:00
Wesley W. Terpstra c9459fe4eb tilelink2 Xbar: don't use unnecessary ports 2017-03-19 17:02:24 -07:00
Wesley W. Terpstra 7971947d6c tilelink2 Monitor: don't inspect bits if valid is forbidden 2017-03-19 16:34:23 -07:00
Wesley W. TerpstraandGitHub a4ca424a22 AHBToTL: finally get the error signal right? (#594) 2017-03-18 22:24:20 -07:00
Wesley W. TerpstraandGitHub d4272db067 travis: only run 4 jobs at once (#593) 
We can only run 4 at a time; 5 causes the test time to double.
In the past we had a 50minute build deadline, but that's fixed.
 2017-03-18 04:14:50 -07:00
Wesley W. TerpstraandGitHub f6daa782d3 AHBToTL: fix the order of updates to d_pause (#592) 2017-03-17 19:34:40 -07:00
Wesley W. TerpstraandGitHub db55a1d755 Fragmenter: fix a bug when underlying device supports larger bursts (#589) 2017-03-17 11:00:49 -07:00
Wesley W. TerpstraandGitHub eb953c40f0 Merge pull request #587 from ucb-bar/ahb-fix 
ahb: rewrote TLToAHB to avoid retracting requests on stall
 2017-03-16 20:55:39 -07:00
Wesley W. Terpstra 9b5b3279a6 AHBToTL: don't report error during idle cycles 2017-03-16 18:18:29 -07:00
Wesley W. Terpstra 5efd38bf97 apb: put both aFlow options under regression 2017-03-16 15:36:14 -07:00
Wesley W. Terpstra 882a7ff8ff TLToAPB: use the now standard aFlow parameter name 2017-03-16 15:34:59 -07:00