commit
d4c9c13fb4
@ -345,7 +345,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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}
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// Finish TileLink transaction by issuing a GrantAck
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grantackq.io.enq.valid := d_done && edge.hasFollowUp(tl_out.d.bits)
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grantackq.io.enq.valid := d_done && edge.isRequest(tl_out.d.bits)
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grantackq.io.enq.bits := edge.GrantAck(tl_out.d.bits)
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tl_out.e <> grantackq.io.deq
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assert(!grantackq.io.enq.valid || grantackq.io.enq.ready, "Too many Grants received by dcache.")
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@ -246,7 +246,7 @@ class MSHR(id: Int)(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCach
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val grantackq = Module(new Queue(io.mem_finish.bits, 1))
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val can_finish = state.isOneOf(s_invalid, s_refill_req)
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grantackq.io.enq.valid := refill_done && edge.hasFollowUp(io.mem_grant.bits)
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grantackq.io.enq.valid := refill_done && edge.isRequest(io.mem_grant.bits)
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grantackq.io.enq.bits := edge.GrantAck(io.mem_grant.bits)
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io.mem_finish.valid := grantackq.io.deq.valid && can_finish
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io.mem_finish.bits := grantackq.io.deq.bits
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@ -40,7 +40,7 @@ class CoreplexLocalInterrupter(address: BigInt = 0x02000000)(implicit p: Paramet
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}
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val node = TLRegisterNode(
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address = AddressSet(address, size-1),
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address = Seq(AddressSet(address, size-1)),
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device = device,
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beatBytes = p(XLen)/8)
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@ -72,7 +72,7 @@ class TLPLIC(maxPriorities: Int, address: BigInt = 0xC000000)(implicit p: Parame
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}
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val node = TLRegisterNode(
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address = AddressSet(address, PLICConsts.size-1),
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address = Seq(AddressSet(address, PLICConsts.size-1)),
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device = device,
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beatBytes = p(XLen)/8,
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undefZero = false)
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@ -57,7 +57,7 @@ class TLEdge(
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}
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}
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def hasFollowUp(x: TLChannel): Bool = {
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def isRequest(x: TLChannel): Bool = {
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x match {
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case a: TLBundleA => Bool(true)
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case b: TLBundleB => Bool(true)
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@ -71,6 +71,18 @@ class TLEdge(
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}
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}
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def isResponse(x: TLChannel): Bool = {
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x match {
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case a: TLBundleA => Bool(false)
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case b: TLBundleB => Bool(false)
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case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
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// opcode =/= TLMessages.Release &&
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// opcode =/= TLMessages.ReleaseData
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case d: TLBundleD => Bool(true) // Grant isResponse + isRequest
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case e: TLBundleE => Bool(true)
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}
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}
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def hasData(x: TLChannel): Bool = {
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val opdata = x match {
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case a: TLBundleA => !a.opcode(2)
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@ -110,10 +110,9 @@ class TLMonitor(args: TLMonitorArgs) extends TLMonitorBase(args)
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when (bundle.opcode === TLMessages.Probe) {
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assert (edge.client.supportsProbe(bundle.source, bundle.size), "'B' channel carries Probe type unsupported by client" + extra)
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assert (address_ok, "'B' channel Probe carries unmanaged address" + extra)
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assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), "'B' channel Probe smaller than a beat" + extra)
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assert (is_aligned, "'B' channel Probe address not aligned to size" + extra)
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assert (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
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assert (~bundle.mask === UInt(0), "'B' channel Probe contains invalid mask" + extra)
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assert (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
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}
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when (bundle.opcode === TLMessages.Get) {
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@ -186,7 +185,6 @@ class TLMonitor(args: TLMonitorArgs) extends TLMonitorBase(args)
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assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), "'C' channel ProbeAckData smaller than a beat" + extra)
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assert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
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assert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
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assert (!bundle.error, "'C' channel ProbeData carries an error" + extra)
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}
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when (bundle.opcode === TLMessages.Release) {
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@ -204,7 +202,6 @@ class TLMonitor(args: TLMonitorArgs) extends TLMonitorBase(args)
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assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), "'C' channel ReleaseData smaller than a beat" + extra)
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assert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
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assert (TLPermissions.isShrink(bundle.param), "'C' channel ReleaseData carries invalid shrink param" + extra)
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assert (!bundle.error, "'C' channel ReleaseData carries an error" + extra)
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}
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when (bundle.opcode === TLMessages.AccessAck) {
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@ -411,34 +408,66 @@ class TLMonitor(args: TLMonitorArgs) extends TLMonitorBase(args)
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}
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}
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def legalizeSourceUnique(bundle: TLBundleSnoop, edge: TLEdge)(implicit sourceInfo: SourceInfo) {
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def legalizeADSource(bundle: TLBundleSnoop, edge: TLEdge)(implicit sourceInfo: SourceInfo) {
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val inflight = RegInit(UInt(0, width = edge.client.endSourceId))
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val a_last = edge.last(bundle.a.bits, bundle.a.fire())
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val d_last = edge.last(bundle.d.bits, bundle.d.fire())
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if (edge.manager.minLatency > 0) {
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assert(bundle.d.bits.opcode === TLMessages.ReleaseAck || bundle.a.bits.source =/= bundle.d.bits.source || !bundle.a.valid || !bundle.d.valid, s"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}" + extra)
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}
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val a_first = edge.first(bundle.a.bits, bundle.a.fire())
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val d_first = edge.first(bundle.d.bits, bundle.d.fire())
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val a_set = Wire(init = UInt(0, width = edge.client.endSourceId))
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when (bundle.a.fire()) {
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when (a_last) { a_set := UIntToOH(bundle.a.bits.source) }
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when (bundle.a.fire() && a_first && edge.isRequest(bundle.a.bits)) {
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a_set := UIntToOH(bundle.a.bits.source)
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assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
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}
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val d_clr = Wire(init = UInt(0, width = edge.client.endSourceId))
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when (bundle.d.fire() && bundle.d.bits.opcode =/= TLMessages.ReleaseAck) {
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when (d_last) { d_clr := UIntToOH(bundle.d.bits.source) }
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val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
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when (bundle.d.fire() && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
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d_clr := UIntToOH(bundle.d.bits.source)
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assert((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
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}
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if (edge.manager.minLatency > 0) {
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assert(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}" + extra)
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}
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inflight := (inflight | a_set) & ~d_clr
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}
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def legalizeDESink(bundle: TLBundleSnoop, edge: TLEdge)(implicit sourceInfo: SourceInfo) {
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val inflight = RegInit(UInt(0, width = edge.manager.endSinkId))
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val d_first = edge.first(bundle.d.bits, bundle.d.fire())
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val e_first = Bool(true)
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val d_set = Wire(init = UInt(0, width = edge.manager.endSinkId))
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when (bundle.d.fire() && d_first && edge.isRequest(bundle.d.bits)) {
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d_set := UIntToOH(bundle.d.bits.sink)
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assert(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
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}
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val e_clr = Wire(init = UInt(0, width = edge.manager.endSinkId))
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when (bundle.e.fire() && e_first && edge.isResponse(bundle.e.bits)) {
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e_clr := UIntToOH(bundle.e.bits.sink)
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assert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
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}
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// edge.client.minLatency applies to BC, not DE
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inflight := (inflight | d_set) & ~e_clr
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}
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def legalizeUnique(bundle: TLBundleSnoop, edge: TLEdge)(implicit sourceInfo: SourceInfo) {
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legalizeADSource(bundle, edge)
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if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
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// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
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legalizeDESink(bundle, edge)
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}
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}
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def legalize(bundle: TLBundleSnoop, edge: TLEdge, reset: Bool) {
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legalizeFormat (bundle, edge)
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legalizeMultibeat (bundle, edge)
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legalizeSourceUnique(bundle, edge)
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legalizeFormat (bundle, edge)
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legalizeMultibeat(bundle, edge)
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legalizeUnique (bundle, edge)
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}
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}
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@ -189,7 +189,7 @@ case class TLClientParameters(
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case class TLClientPortParameters(
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clients: Seq[TLClientParameters],
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unsafeAtomics: Boolean = false,
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minLatency: Int = 0) // Atomics are executed as get+put
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minLatency: Int = 0) // Only applies to B=>C
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{
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require (!clients.isEmpty)
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require (minLatency >= 0)
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@ -9,7 +9,7 @@ import regmapper._
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import scala.math.{min,max}
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class TLRegisterNode(
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address: AddressSet,
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address: Seq[AddressSet],
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device: Device,
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deviceKey: String = "reg",
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concurrency: Int = 0,
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@ -18,7 +18,7 @@ class TLRegisterNode(
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executable: Boolean = false)
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extends TLManagerNode(Seq(TLManagerPortParameters(
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Seq(TLManagerParameters(
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address = Seq(address),
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address = address,
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resources = Seq(Resource(device, deviceKey)),
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executable = executable,
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supportsGet = TransferSizes(1, beatBytes),
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@ -28,7 +28,12 @@ class TLRegisterNode(
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beatBytes = beatBytes,
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minLatency = min(concurrency, 1)))) // the Queue adds at most one cycle
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{
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require (address.contiguous)
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val size = 1 << log2Ceil(1 + address.map(_.max).max - address.map(_.base).min)
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require (size >= beatBytes)
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address.foreach { case a =>
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require (a.widen(size-1).base == address.head.widen(size-1).base,
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s"TLRegisterNode addresses (${address}) must be aligned to its size ${size}")
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}
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// Calling this method causes the matching TL2 bundle to be
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// configured to route all requests to the listed RegFields.
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@ -43,7 +48,7 @@ class TLRegisterNode(
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val (sourceEnd, sourceOff) = (edge.bundle.sourceBits + sizeEnd, sizeEnd)
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val (addrLoEnd, addrLoOff) = (log2Up(beatBytes) + sourceEnd, sourceEnd)
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val params = RegMapperParams(log2Up((address.mask+1)/beatBytes), beatBytes, addrLoEnd)
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val params = RegMapperParams(log2Up(size/beatBytes), beatBytes, addrLoEnd)
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val in = Wire(Decoupled(new RegMapperInput(params)))
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in.bits.read := a.bits.opcode === TLMessages.Get
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in.bits.index := edge.addr_hi(a.bits)
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@ -81,7 +86,7 @@ class TLRegisterNode(
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object TLRegisterNode
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{
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def apply(
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address: AddressSet,
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address: Seq[AddressSet],
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device: Device,
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deviceKey: String = "reg",
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concurrency: Int = 0,
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@ -98,7 +103,7 @@ object TLRegisterNode
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abstract class TLRegisterRouterBase(devname: String, devcompat: Seq[String], val address: AddressSet, interrupts: Int, concurrency: Int, beatBytes: Int, undefZero: Boolean, executable: Boolean)(implicit p: Parameters) extends LazyModule
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{
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val device = new SimpleDevice(devname, devcompat)
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val node = TLRegisterNode(address, device, "reg", concurrency, beatBytes, undefZero, executable)
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val node = TLRegisterNode(Seq(address), device, "reg", concurrency, beatBytes, undefZero, executable)
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val intnode = IntSourceNode(IntSourcePortSimple(num = interrupts, resources = Seq(Resource(device, "int"))))
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}
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Loading…
Reference in New Issue
Block a user