riscv/rocket-chip
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bootrom: also setup SBI a0+a1 for when we hang (#617)

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This way a program started by the debugger still has the DTB handy.
This commit is contained in:
Wesley W. Terpstra 2017-03-27 00:01:05 -07:00 committed by GitHub
parent 11507ac7d6
commit 722b0d521f
3 changed files with 8 additions and 4 deletions
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9
bootrom/bootrom.S
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@ -1,7 +1,9 @@
#define DRAM_BASE 0x80000000
.section .text.start, "ax", @progbits
.globl _start
_start:
la s0, DRAM_BASE
li s0, DRAM_BASE
csrr a0, mhartid
la a1, _dtb
jr s0
@ -9,8 +11,11 @@ _start:
.section .text.hang, "ax", @progbits
.globl _hang
_hang:
csrr a0, mhartid
la a1, _dtb
1:
wfi
j _hang
j 1b
.section .rodata.dtb, "a", @progbits
.globl _dtb

BIN
bootrom/bootrom.img
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3
bootrom/linker.ld
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@ -1,7 +1,6 @@
SECTIONS
{
DRAM_BASE = 0x80000000;
ROM_BASE = 0x10000;
ROM_BASE = 0x10000; /* ... but actually position independent */
. = ROM_BASE;
.text.start : { *(.text.start) }