riscv/rocket-chip
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Merge pull request #595 from ucb-bar/ignore-tl-c

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Ignore TL-C
This commit is contained in:
Wesley W. Terpstra 2017-03-19 18:49:11 -07:00 committed by GitHub
commit 5a50acfd9d
3 changed files with 49 additions and 14 deletions
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1
src/main/scala/rocket/ICache.scala
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@ -156,6 +156,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
fromSource = UInt(0),
toAddress = (refill_addr >> blockOffBits) << blockOffBits,
lgSize = lgCacheBlockBytes)._2
tl_out.b.ready := Bool(true)
tl_out.c.valid := Bool(false)
tl_out.e.valid := Bool(false)

18
src/main/scala/uncore/tilelink2/Monitor.scala
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@ -295,10 +295,16 @@ class TLMonitor(args: TLMonitorArgs) extends TLMonitorBase(args)
def legalizeFormat(bundle: TLBundleSnoop, edge: TLEdge)(implicit sourceInfo: SourceInfo) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
assert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
assert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
assert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledSnoop[TLBundleA], edge: TLEdge)(implicit sourceInfo: SourceInfo) {
@ -398,9 +404,11 @@ class TLMonitor(args: TLMonitorArgs) extends TLMonitorBase(args)
def legalizeMultibeat(bundle: TLBundleSnoop, edge: TLEdge)(implicit sourceInfo: SourceInfo) {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
def legalizeSourceUnique(bundle: TLBundleSnoop, edge: TLEdge)(implicit sourceInfo: SourceInfo) {

44
src/main/scala/uncore/tilelink2/Xbar.scala
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@ -103,24 +103,50 @@ class TLXbar(policy: TLArbiter.Policy = TLArbiter.lowestIndexFirst)(implicit p:
val in = Wire(Vec(io.in.size, TLBundle(wide_bundle)))
for (i <- 0 until in.size) {
val r = inputIdRanges(i)
in(i) <> io.in(i)
// prefix sources
in(i).a <> io.in(i).a
io.in(i).d <> in(i).d
in(i).a.bits.source := io.in(i).a.bits.source | UInt(r.start)
in(i).c.bits.source := io.in(i).c.bits.source | UInt(r.start)
// defix sources
io.in(i).b.bits.source := trim(in(i).b.bits.source, r.size)
io.in(i).d.bits.source := trim(in(i).d.bits.source, r.size)
if (node.edgesIn(i).client.anySupportProbe && node.edgesOut.exists(_.manager.anySupportAcquireB)) {
in(i).c <> io.in(i).c
in(i).e <> io.in(i).e
io.in(i).b <> in(i).b
in(i).c.bits.source := io.in(i).c.bits.source | UInt(r.start)
io.in(i).b.bits.source := trim(in(i).b.bits.source, r.size)
} else {
in(i).c.valid := Bool(false)
in(i).e.valid := Bool(false)
in(i).b.ready := Bool(false)
io.in(i).c.ready := Bool(true)
io.in(i).e.ready := Bool(true)
io.in(i).b.valid := Bool(false)
}
}
// Transform output bundle sinks (sources use global namespace on both sides)
val out = Wire(Vec(io.out.size, TLBundle(wide_bundle)))
for (i <- 0 until out.size) {
val r = outputIdRanges(i)
io.out(i) <> out(i)
// prefix sinks
io.out(i).a <> out(i).a
out(i).d <> io.out(i).d
out(i).d.bits.sink := io.out(i).d.bits.sink | UInt(r.start)
// defix sinks
io.out(i).e.bits.sink := trim(out(i).e.bits.sink, r.size)
if (node.edgesOut(i).manager.anySupportAcquireB && node.edgesIn.exists(_.client.anySupportProbe)) {
io.out(i).c <> out(i).c
io.out(i).e <> out(i).e
out(i).b <> io.out(i).b
io.out(i).e.bits.sink := trim(out(i).e.bits.sink, r.size)
} else {
out(i).c.ready := Bool(false)
out(i).e.ready := Bool(false)
out(i).b.valid := Bool(false)
io.out(i).c.valid := Bool(false)
io.out(i).e.valid := Bool(false)
io.out(i).b.ready := Bool(true)
}
}
val addressA = (in zip node.edgesIn) map { case (i, e) => e.address(i.a.bits) }