Yunsup Lee
|
93df795e48
|
change LLC leaf SRAM size
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2013-04-22 11:06:50 -07:00 |
|
Andrew Waterman
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7f5282d355
|
replace RDNPC with AUIPC
|
2013-04-22 04:21:46 -07:00 |
|
Andrew Waterman
|
50ccc20bf3
|
replace RDNPC with AUIPC
|
2013-04-22 04:20:15 -07:00 |
|
Huy Vo
|
2ac3fd5306
|
get rid of init_node
|
2013-04-20 01:36:32 -07:00 |
|
Huy Vo
|
0d87e3bacc
|
fixed init pin generation
|
2013-04-20 00:38:01 -07:00 |
|
Henry Cook
|
a01cdf95fd
|
tell physical networks carring cache lines to lock arbitration for REFILL_CYCLES pumps
|
2013-04-10 13:53:27 -07:00 |
|
Henry Cook
|
db5a060c7d
|
fix io dir
|
2013-04-10 13:47:30 -07:00 |
|
Henry Cook
|
766d5622b1
|
Prevent messages from becoming interleaved in the BasicCrossbar. Remove dependency trackers from the uncore, use msg headers instead. Have one ReleaseHnadler per core for now.
|
2013-04-10 13:46:31 -07:00 |
|
Henry Cook
|
d7982bf27f
|
bump uncore for grant fix
|
2013-04-09 14:29:49 -07:00 |
|
Henry Cook
|
74187c2068
|
Always route voluntary releases to ReleaseTracker to ensure all grants are sent
|
2013-04-09 14:09:55 -07:00 |
|
Andrew Waterman
|
7ea782fd22
|
add LR/SC
|
2013-04-07 19:36:15 -07:00 |
|
Andrew Waterman
|
ae7720e284
|
guarantee LR/SC forward progress
the mechanism is to block new probes for several cycles after a successful LR.
this also cleans up the MSHR <-> ProbeUnit interface slightly.
|
2013-04-07 19:27:21 -07:00 |
|
Andrew Waterman
|
7ff5b5b86f
|
treat load-reserved as a non-dirtying store
|
2013-04-07 19:25:26 -07:00 |
|
Andrew Waterman
|
3479f1c6cd
|
add LR/SC support
|
2013-04-07 19:25:20 -07:00 |
|
Andrew Waterman
|
e74e032c87
|
simplify MSHR memory response logic
|
2013-04-06 01:03:37 -07:00 |
|
Andrew Waterman
|
1abb9277db
|
fix LR/SC atomicity violation
note, it's still not starvation-free.
|
2013-04-05 19:13:38 -07:00 |
|
Andrew Waterman
|
8cbdeb2abf
|
add LR/SC support
|
2013-04-04 17:07:09 -07:00 |
|
Andrew Waterman
|
fc46daecf6
|
don't flush pipeline on writes to side-effect-free PCRs
notably, K0, K1, and EPC
|
2013-04-04 17:07:09 -07:00 |
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Andrew Waterman
|
8b439ef20d
|
only support setpcr/clearpcr of SR
the full PCR RMW support was wasted area/power
|
2013-04-04 17:07:08 -07:00 |
|
Andrew Waterman
|
d43f484feb
|
take interrupts on nonzero fromhost values
|
2013-04-04 17:07:08 -07:00 |
|
Andrew Waterman
|
d4a3351cfc
|
expose pending interrupts in status register
|
2013-04-04 17:07:08 -07:00 |
|
Henry Cook
|
c6b56c5f25
|
bump rocket for coherence bug fix
|
2013-04-04 15:52:20 -07:00 |
|
Henry Cook
|
f8aebcbf8c
|
fix for cache controller bug: failing to mux correct metadata into mshr.io.old_meta on tag match
|
2013-04-04 15:50:29 -07:00 |
|
Henry Cook
|
9d5e97d89e
|
override io in LogicalNetwork
|
2013-03-28 14:10:20 -07:00 |
|
Henry Cook
|
b6cc08e8ca
|
override io in LogicalNetwork
|
2013-03-28 14:09:48 -07:00 |
|
Henry Cook
|
16ad8a7e9c
|
Fixes after merge
|
2013-03-25 19:14:38 -07:00 |
|
Henry Cook
|
67fc09f62e
|
Fixes after merge, and always self probe.
|
2013-03-25 19:12:19 -07:00 |
|
Henry Cook
|
16113a96ba
|
fixes after merge
|
2013-03-25 19:09:08 -07:00 |
|
Andrew Waterman
|
8e926f8d79
|
remove aborts
|
2013-03-25 17:01:46 -07:00 |
|
Henry Cook
|
eec590c1bf
|
Added support for multiple L2 banks. Moved tile IO queueing.
|
2013-03-25 17:01:46 -07:00 |
|
Henry Cook
|
806f897fc4
|
nTiles -> nClients in LogicalNetworkConfig
|
2013-03-25 17:01:46 -07:00 |
|
Andrew Waterman
|
ce4c1aa566
|
remove aborts
|
2013-03-25 17:01:46 -07:00 |
|
Henry Cook
|
cf76665d09
|
writebacks on release network pass asm tests and bmarks
|
2013-03-25 17:01:46 -07:00 |
|
Henry Cook
|
a0dc8d52d6
|
using new network and l2 controller
|
2013-03-25 17:01:46 -07:00 |
|
Andrew Waterman
|
def11e44b8
|
don't pipe stdout to vcd2vpd
|
2013-03-25 17:01:13 -07:00 |
|
Andrew Waterman
|
ef4927c9ad
|
use a named pipe for VCD -> VPD conversion
|
2013-03-25 16:19:19 -07:00 |
|
Henry Cook
|
06f5de3b68
|
Merge branch 'release-xacts'
Conflicts:
src/package.scala
src/uncore.scala
|
2013-03-20 17:38:46 -07:00 |
|
Henry Cook
|
95f0a688e9
|
Merge branch 'release-xacts'
Conflicts:
src/htif.scala
src/icache.scala
src/nbdcache.scala
src/tile.scala
|
2013-03-20 17:37:50 -07:00 |
|
Henry Cook
|
4d007d5c40
|
changed val names in hub to match new tilelink names
|
2013-03-20 17:14:07 -07:00 |
|
Henry Cook
|
273bd34091
|
Generalized mem arbiter, moved to uncore. Support for multiple banks when acking grants.
|
2013-03-20 15:53:36 -07:00 |
|
Henry Cook
|
c36b1dfa30
|
Cleaned up uncore and coherence interface. Removed defunct broadcast hub. Trait-ified tilelink bundle components. Added generalized mem arbiter.
|
2013-03-20 15:52:39 -07:00 |
|
Henry Cook
|
319b4544d7
|
nTiles -> nClients in LogicalNetworkConfig
|
2013-03-20 14:30:16 -07:00 |
|
Henry Cook
|
a7ae7e5758
|
Cleaned up self-probes
|
2013-03-20 14:28:20 -07:00 |
|
Henry Cook
|
6d2541aced
|
nTiles -> nClients in LogicalNetworkConfig
|
2013-03-20 14:12:36 -07:00 |
|
Andrew Waterman
|
7b019cb0da
|
rmeove aborts
|
2013-03-19 15:30:23 -07:00 |
|
Andrew Waterman
|
ea9d0b771e
|
remove aborts; simplify probes
|
2013-03-19 15:29:40 -07:00 |
|
Yunsup Lee
|
bc140ce9bc
|
add vec_{vvadd,cmplxmult,matmul} bmarks
|
2013-03-19 00:43:51 -07:00 |
|
Yunsup Lee
|
9efe71412f
|
add DRAMSideLLCNull
|
2013-03-19 00:43:34 -07:00 |
|
Yunsup Lee
|
0f50970913
|
move HellaQueue to uncore
|
2013-03-19 00:43:20 -07:00 |
|
Yunsup Lee
|
f120800aa2
|
add DRAMSideLLCNull
|
2013-03-19 00:41:28 -07:00 |
|