Andrew Waterman
|
cc0f8962fb
|
[rocket] take physical memory attribute check off critical path
Cache the attributes in the TLB instead.
|
2016-08-02 17:21:03 -07:00 |
|
Andrew Waterman
|
832e56d3c7
|
Fix toBits/toUInt/toSInt deprecation warnings
|
2016-07-31 17:13:52 -07:00 |
|
Andrew Waterman
|
1699622730
|
Don't speculatively refill I$ in uncacheable regions
|
2016-07-09 01:10:58 -07:00 |
|
Andrew Waterman
|
8bd7e3932b
|
Implement priv-1.9 PTE scheme
|
2016-07-05 19:19:49 -07:00 |
|
Andrew Waterman
|
663002ec0c
|
Improve TLB simulation performance
|
2016-07-02 14:26:05 -07:00 |
|
Howard Mao
|
a9e0a5e2df
|
changes to imports after uncore refactor
|
2016-06-28 14:09:31 -07:00 |
|
Andrew Waterman
|
60bddddfe6
|
Merge sptbr and sasid
|
2016-06-17 18:29:05 -07:00 |
|
Andrew Waterman
|
9949347569
|
First stab at debug interrupts
|
2016-06-01 16:57:10 -07:00 |
|
Andrew Waterman
|
3ee5144923
|
Fix TLB tag check logic when ASIDs are present
|
2016-05-27 12:24:17 -07:00 |
|
Andrew Waterman
|
5352497edb
|
MPRV takes effect regardless of privilege mode
|
2016-05-02 19:53:25 -07:00 |
|
Andrew Waterman
|
5af98145b9
|
don't signal bad physical address on TLB miss
|
2016-04-30 17:31:46 -07:00 |
|
Andrew Waterman
|
70664bbca0
|
Fix Chisel3 build for UseVM=false
|
2016-03-30 22:48:31 -07:00 |
|
Andrew Waterman
|
a4685a073f
|
Don't instantiate PTW when UseVM=false
|
2016-03-25 14:17:25 -07:00 |
|
Andrew Waterman
|
7ae44d4905
|
Add RV32 support
|
2016-03-10 17:32:00 -08:00 |
|
Andrew Waterman
|
bc15e8649e
|
WIP on priv spec v1.9
|
2016-03-02 23:29:58 -08:00 |
|
Howard Mao
|
305185c034
|
send DMA requests through MMIO and get responses through CSRs
|
2016-01-29 14:51:56 -08:00 |
|
Howard Mao
|
120361226d
|
fix more Chisel3 deprecations
|
2016-01-14 14:46:31 -08:00 |
|
Albert Magyar
|
01a3447989
|
Remove duplicate PseudoLRU class from rocket TLB
|
2015-12-16 16:12:47 -08:00 |
|
Henry Cook
|
4f8468b60f
|
depend on external cde library
|
2015-10-21 18:19:23 -07:00 |
|
Henry Cook
|
4508666d96
|
log2ceil
|
2015-10-06 18:22:47 -07:00 |
|
Henry Cook
|
8173695800
|
added HasAddrMapParameters
|
2015-10-06 18:22:40 -07:00 |
|
Henry Cook
|
84576650b5
|
Removed all traces of params
|
2015-10-05 21:48:05 -07:00 |
|
Henry Cook
|
69a4dd0a79
|
refactor NASTI to not use param
|
2015-10-02 14:20:47 -07:00 |
|
Andrew Waterman
|
833909a2b5
|
Chisel3 compatibility fixes
|
2015-09-30 14:36:26 -07:00 |
|
Howard Mao
|
4bda6b6757
|
fix bug in tlb refill
|
2015-09-26 21:27:36 -07:00 |
|
Howard Mao
|
6bf8f41cef
|
make sure passthrough requests are treated as vm_enabled = false
|
2015-09-26 20:29:51 -07:00 |
|
Howard Mao
|
9eb988a4c6
|
make sure access to invalid physical address treated as exception
|
2015-09-22 10:11:43 -07:00 |
|
Andrew Waterman
|
6c0e1e33ab
|
Purge UInt := SInt assignments
|
2015-07-31 15:42:10 -07:00 |
|
Andrew Waterman
|
57930e8a26
|
Chisel3 compatibility potpourri
|
2015-07-30 23:53:02 -07:00 |
|
Henry Cook
|
d2a594fb57
|
new junctions repo has mem size constants
|
2015-07-29 18:05:54 -07:00 |
|
Andrew Waterman
|
ce161b83e3
|
Chisel3 compatibility: avoid subword assignment
|
2015-07-29 15:03:13 -07:00 |
|
Andrew Waterman
|
5b7f3c3006
|
Don't use clone
|
2015-07-15 17:30:50 -07:00 |
|
Andrew Waterman
|
f460cb6c54
|
Update to privileged architecture 1.7
|
2015-05-19 02:32:21 -07:00 |
|
Andrew Waterman
|
d912ea265e
|
New virtual memory implementation (Sv39)
|
2015-03-27 16:20:59 -07:00 |
|
Andrew Waterman
|
0332c1e7fe
|
Reduce latency of page table walks
A small cache in the PTW caches non-leaf PTEs, reducing latency and D$ misses.
|
2015-03-24 18:58:38 -07:00 |
|
Andrew Waterman
|
e85c54cc4b
|
New privileged ISA implementation
|
2015-03-14 02:49:07 -07:00 |
|
Henry Cook
|
aa46b8b72d
|
Slightly refactor TLBResp
|
2015-02-03 19:32:37 -08:00 |
|
Henry Cook
|
741e6b77ad
|
Rename some params, use refactored TileLink
|
2015-02-01 20:37:31 -08:00 |
|
Yunsup Lee
|
8abf62fae3
|
add LICENSE
|
2014-09-12 18:06:41 -07:00 |
|
Henry Cook
|
0dac9a7467
|
Full conversion to params. Compiles but does not elaborate.
|
2014-08-19 11:38:02 -07:00 |
|
Andrew Waterman
|
cbb37ccc3e
|
Use Mem instead of Vec[Reg]
|
2014-05-18 19:25:43 -07:00 |
|
Andrew Waterman
|
4ca152b012
|
Use BundleWithConf to avoid clone method boilerplate
|
2014-05-09 19:37:16 -07:00 |
|
Henry Cook
|
910b3b203a
|
removed AddressSpaceConstants, CacheConstants, and TileLinkSizeConstants
|
2014-04-10 12:32:44 -07:00 |
|
Andrew Waterman
|
e8486817e6
|
Clean up formatting (i.e. remove tabs, semicolons)
|
2014-01-13 21:43:56 -08:00 |
|
Andrew Waterman
|
53f726008b
|
Use Mem instead of Vec[Reg] for TLB
QoR-neutral, improves simulation speed
|
2013-11-24 14:21:02 -08:00 |
|
Henry Cook
|
d06e24ac24
|
new enum syntax
|
2013-09-10 10:51:35 -07:00 |
|
Andrew Waterman
|
52e31f3298
|
Bypass scoreboard updates
This reduces div/mul/D$ miss latency by 1 cycle.
|
2013-08-24 14:44:04 -07:00 |
|
Andrew Waterman
|
d4a0db4575
|
Reflect ISA changes
|
2013-08-24 14:43:55 -07:00 |
|
Henry Cook
|
3a266cbbfa
|
final Reg changes
|
2013-08-15 15:28:15 -07:00 |
|
Henry Cook
|
1a9e43aa11
|
initial attempt at upgrade
|
2013-08-12 10:39:11 -07:00 |
|