 Howard Mao
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d34e790ac0
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get rid of duplicated code in rocket Util
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2016-08-18 18:40:07 -07:00 |
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Howard Mao
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2645f74af2
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clean up addrmap flatten function
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2016-08-09 22:14:32 -07:00 |
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 Andrew Waterman
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cc0f8962fb
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[rocket] take physical memory attribute check off critical path
Cache the attributes in the TLB instead.
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2016-08-02 17:21:03 -07:00 |
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Andrew Waterman
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832e56d3c7
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Fix toBits/toUInt/toSInt deprecation warnings
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2016-07-31 17:13:52 -07:00 |
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Andrew Waterman
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1699622730
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Don't speculatively refill I$ in uncacheable regions
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2016-07-09 01:10:58 -07:00 |
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Andrew Waterman
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8bd7e3932b
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Implement priv-1.9 PTE scheme
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2016-07-05 19:19:49 -07:00 |
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Andrew Waterman
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663002ec0c
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Improve TLB simulation performance
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2016-07-02 14:26:05 -07:00 |
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Howard Mao
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a9e0a5e2df
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changes to imports after uncore refactor
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2016-06-28 14:09:31 -07:00 |
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Andrew Waterman
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60bddddfe6
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Merge sptbr and sasid
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2016-06-17 18:29:05 -07:00 |
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Andrew Waterman
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9949347569
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First stab at debug interrupts
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2016-06-01 16:57:10 -07:00 |
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Andrew Waterman
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3ee5144923
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Fix TLB tag check logic when ASIDs are present
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2016-05-27 12:24:17 -07:00 |
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Andrew Waterman
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5352497edb
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MPRV takes effect regardless of privilege mode
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2016-05-02 19:53:25 -07:00 |
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Andrew Waterman
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5af98145b9
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don't signal bad physical address on TLB miss
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2016-04-30 17:31:46 -07:00 |
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Andrew Waterman
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70664bbca0
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Fix Chisel3 build for UseVM=false
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2016-03-30 22:48:31 -07:00 |
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Andrew Waterman
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a4685a073f
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Don't instantiate PTW when UseVM=false
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2016-03-25 14:17:25 -07:00 |
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Andrew Waterman
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7ae44d4905
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Add RV32 support
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2016-03-10 17:32:00 -08:00 |
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Andrew Waterman
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bc15e8649e
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WIP on priv spec v1.9
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2016-03-02 23:29:58 -08:00 |
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Howard Mao
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305185c034
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send DMA requests through MMIO and get responses through CSRs
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2016-01-29 14:51:56 -08:00 |
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Howard Mao
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120361226d
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fix more Chisel3 deprecations
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2016-01-14 14:46:31 -08:00 |
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 Albert Magyar
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01a3447989
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Remove duplicate PseudoLRU class from rocket TLB
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2015-12-16 16:12:47 -08:00 |
|
 Henry Cook
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4f8468b60f
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depend on external cde library
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2015-10-21 18:19:23 -07:00 |
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Henry Cook
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4508666d96
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log2ceil
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2015-10-06 18:22:47 -07:00 |
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Henry Cook
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8173695800
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added HasAddrMapParameters
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2015-10-06 18:22:40 -07:00 |
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Henry Cook
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84576650b5
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Removed all traces of params
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2015-10-05 21:48:05 -07:00 |
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Henry Cook
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69a4dd0a79
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refactor NASTI to not use param
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2015-10-02 14:20:47 -07:00 |
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Andrew Waterman
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833909a2b5
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Chisel3 compatibility fixes
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2015-09-30 14:36:26 -07:00 |
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Howard Mao
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4bda6b6757
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fix bug in tlb refill
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2015-09-26 21:27:36 -07:00 |
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Howard Mao
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6bf8f41cef
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make sure passthrough requests are treated as vm_enabled = false
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2015-09-26 20:29:51 -07:00 |
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Howard Mao
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9eb988a4c6
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make sure access to invalid physical address treated as exception
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2015-09-22 10:11:43 -07:00 |
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Andrew Waterman
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6c0e1e33ab
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Purge UInt := SInt assignments
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2015-07-31 15:42:10 -07:00 |
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Andrew Waterman
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57930e8a26
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Chisel3 compatibility potpourri
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2015-07-30 23:53:02 -07:00 |
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Henry Cook
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d2a594fb57
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new junctions repo has mem size constants
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2015-07-29 18:05:54 -07:00 |
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Andrew Waterman
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ce161b83e3
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Chisel3 compatibility: avoid subword assignment
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2015-07-29 15:03:13 -07:00 |
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Andrew Waterman
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5b7f3c3006
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Don't use clone
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2015-07-15 17:30:50 -07:00 |
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Andrew Waterman
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f460cb6c54
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Update to privileged architecture 1.7
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2015-05-19 02:32:21 -07:00 |
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Andrew Waterman
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d912ea265e
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New virtual memory implementation (Sv39)
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2015-03-27 16:20:59 -07:00 |
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Andrew Waterman
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0332c1e7fe
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Reduce latency of page table walks
A small cache in the PTW caches non-leaf PTEs, reducing latency and D$ misses.
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2015-03-24 18:58:38 -07:00 |
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Andrew Waterman
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e85c54cc4b
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New privileged ISA implementation
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2015-03-14 02:49:07 -07:00 |
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Henry Cook
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aa46b8b72d
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Slightly refactor TLBResp
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2015-02-03 19:32:37 -08:00 |
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Henry Cook
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741e6b77ad
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Rename some params, use refactored TileLink
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2015-02-01 20:37:31 -08:00 |
|
 Yunsup Lee
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8abf62fae3
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add LICENSE
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2014-09-12 18:06:41 -07:00 |
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Henry Cook
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0dac9a7467
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Full conversion to params. Compiles but does not elaborate.
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2014-08-19 11:38:02 -07:00 |
|
 Andrew Waterman
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cbb37ccc3e
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Use Mem instead of Vec[Reg]
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2014-05-18 19:25:43 -07:00 |
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Andrew Waterman
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4ca152b012
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Use BundleWithConf to avoid clone method boilerplate
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2014-05-09 19:37:16 -07:00 |
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Henry Cook
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910b3b203a
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removed AddressSpaceConstants, CacheConstants, and TileLinkSizeConstants
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2014-04-10 12:32:44 -07:00 |
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Andrew Waterman
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e8486817e6
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Clean up formatting (i.e. remove tabs, semicolons)
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2014-01-13 21:43:56 -08:00 |
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Andrew Waterman
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53f726008b
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Use Mem instead of Vec[Reg] for TLB
QoR-neutral, improves simulation speed
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2013-11-24 14:21:02 -08:00 |
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Henry Cook
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d06e24ac24
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new enum syntax
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2013-09-10 10:51:35 -07:00 |
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Andrew Waterman
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52e31f3298
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Bypass scoreboard updates
This reduces div/mul/D$ miss latency by 1 cycle.
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2013-08-24 14:44:04 -07:00 |
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Andrew Waterman
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d4a0db4575
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Reflect ISA changes
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2013-08-24 14:43:55 -07:00 |
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