Andrew Waterman
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0f092b9b59
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Remove IPI network
This is now provided via MMIO.
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2015-11-16 21:51:43 -08:00 |
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Henry Cook
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0290635454
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amo_shift_bits -> amo_shift_bytes
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2015-11-16 19:07:58 -08:00 |
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Henry Cook
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485f1b7bd7
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bump uncore
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2015-11-16 18:14:03 -08:00 |
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Henry Cook
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64aaf71b06
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L2AcquireTracker refactor to support merging Gets and Puts into Prefetches of the correct type.
Transaction metadata for primary and seconday misses now stored in the secondary miss queue.
Added BuiltInAcquireBuilder factory.
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2015-11-16 18:10:09 -08:00 |
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Henry Cook
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03fa06e6e7
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fix prefetch lockup on L2 hit
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2015-11-15 12:51:34 -08:00 |
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Yunsup Lee
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5e2698adbc
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Merge remote-tracking branch 'origin/master' into rocc-fpu-port
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2015-11-14 16:44:55 -08:00 |
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Yunsup Lee
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8916c7e99c
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push rocket
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2015-11-14 16:43:28 -08:00 |
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Yunsup Lee
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213c1a4c81
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fix fdiv/fsqrt control bug in fpu
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2015-11-14 16:43:15 -08:00 |
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Yunsup Lee
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4dd097d156
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Merge remote-tracking branch 'origin/master' into rocc-fpu-port
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2015-11-14 14:52:13 -08:00 |
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Yunsup Lee
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6a6371fdb6
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move to new version of hardfloat
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2015-11-14 14:50:13 -08:00 |
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Yunsup Lee
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3c3c946755
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move to new version of hardfloat
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2015-11-14 14:49:17 -08:00 |
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Howard Mao
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e12efab423
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skip meta_write state if no meta write pending
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2015-11-13 13:50:35 -08:00 |
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Yunsup Lee
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608e4b2851
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Merge remote-tracking branch 'origin/master' into rocc-fpu-port
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2015-11-12 20:44:25 -08:00 |
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Howard Mao
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a1063bad54
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fix issues with non-allocating put/get
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2015-11-12 15:54:34 -08:00 |
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Howard Mao
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19daee10f0
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use default constructors for IOMSHR acquire construction
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2015-11-12 15:54:05 -08:00 |
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Howard Mao
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7e7d688a01
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make sure L2 passes no-alloc acquires through to outer memory
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2015-11-12 15:40:58 -08:00 |
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Howard Mao
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b3865c370a
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make sure correct addr_beat is sent for Get response by narrower/converter
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2015-11-12 15:40:38 -08:00 |
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Howard Mao
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f397d61033
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add alloc option to Put constructor
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2015-11-12 11:39:59 -08:00 |
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Howard Mao
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7733fbe6a3
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make sure no-alloc write still updates data array if there is a cache hit
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2015-11-12 11:39:36 -08:00 |
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Howard Mao
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10f4c6c71c
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interleave cached and uncached requests
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2015-11-12 11:34:44 -08:00 |
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Colin Schmidt
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97d0e195ae
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Merge pull request #28 from ucb-bar/yusnup
Don't re-generate the .d files on "make clean"
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2015-11-12 00:46:21 -08:00 |
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Palmer Dabbelt
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07f0e6be94
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Don't re-generate the .d files on "make clean"
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2015-11-12 00:41:55 -08:00 |
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Howard Mao
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7cae6cedf5
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finished bit should be set true if generator not being used
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2015-11-11 18:51:16 -08:00 |
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Howard Mao
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f93872d6b4
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make sure cached generator actually drives finished signal
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2015-11-11 18:45:36 -08:00 |
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Howard Mao
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eeda3dd770
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add README
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2015-11-11 18:30:19 -08:00 |
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Howard Mao
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9482d944ca
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make Uncached generator vary the alloc bit
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2015-11-11 18:26:56 -08:00 |
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Howard Mao
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6ddf81090b
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didn't mean to turn off GenerateCached in last commit
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2015-11-11 17:39:08 -08:00 |
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Howard Mao
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11f0b3d8db
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restore old L2 cache AcquireTransactor configuration
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2015-11-11 17:10:58 -08:00 |
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Howard Mao
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31da692ccc
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default to single tile in WithMemtest
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2015-11-11 14:54:13 -08:00 |
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Howard Mao
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55581195eb
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add groundtest submodule for simple memory testing
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2015-11-11 14:33:02 -08:00 |
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Howard Mao
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8a6b231b08
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explicitly configure the number of requests being sent by generators
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2015-11-11 14:32:19 -08:00 |
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Howard Mao
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149480411e
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make sure ClientTileLinkEnqueuer uses the correct parameters
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2015-11-10 16:09:19 -08:00 |
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Howard Mao
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b59ce5fed4
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make sure L2 waits for outer grant before sending grant for write request
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2015-11-10 16:06:14 -08:00 |
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Howard Mao
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13f62e0364
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make sure generators can detect lockup
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2015-11-10 14:39:56 -08:00 |
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Howard Mao
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520925c207
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fix up build.sbt and add gitignore
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2015-11-10 13:38:39 -08:00 |
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Howard Mao
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51f128ec74
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actually use backendBuffering in front of unwrapper/converter chain
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2015-11-09 11:50:18 -08:00 |
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Howard Mao
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42d3d09d7a
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add a ClientTileLinkEnqueuer to complement the TileLinkEnqueuer
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2015-11-09 11:49:19 -08:00 |
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Howard Mao
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7942be4e01
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make sure outerTL method is idempotent
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2015-11-09 11:10:02 -08:00 |
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Andrew Waterman
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59ca373146
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Merge pull request #18 from jackkoenig/master
Fix SimpleHellaCacheIF assumption about receiving rejected request ba…
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2015-11-08 22:38:01 -08:00 |
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jackkoenig
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1e259a55da
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Fix SimpleHellaCacheIF assumption about receiving rejected request back 2 cycles later
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2015-11-08 21:16:31 -08:00 |
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Yunsup Lee
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df5daaa72e
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Merge remote-tracking branch 'origin/master' into rocc-fpu-port
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2015-11-06 23:57:42 -08:00 |
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Andrew Waterman
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2f515b2af6
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Reduce critical path for fdiv valid signal
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2015-11-06 23:28:31 -08:00 |
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Henry Cook
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e3efc09b5b
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remove unnecessary UInt encode/decode on releaseMatches path
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2015-11-05 17:20:03 -08:00 |
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Yunsup Lee
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1e772daeea
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no spaces in Makefrag
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2015-11-05 16:42:05 -08:00 |
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Howard Mao
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cb0c2df051
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update fpga-zynq
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2015-11-05 10:50:13 -08:00 |
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Howard Mao
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42e7067400
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bump uncore
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2015-11-05 10:49:25 -08:00 |
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Howard Mao
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bbf14ddc01
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use definitions in consts header whenever possible
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2015-11-05 10:48:32 -08:00 |
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Howard Mao
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fb501e75c0
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fixes for sub-block TL requests in uncore
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2015-11-05 10:48:32 -08:00 |
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Howard Mao
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7b252d8f89
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get rid of now-unnecessary bits in MIF tag
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2015-11-05 10:48:32 -08:00 |
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Howard Mao
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ba5a6af05c
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correctly stripe data across memory channels in simulation
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2015-11-05 10:48:32 -08:00 |
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