Andrew Waterman
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e85c54cc4b
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New privileged ISA implementation
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2015-03-14 02:49:07 -07:00 |
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Yunsup Lee
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8abf62fae3
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add LICENSE
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2014-09-12 18:06:41 -07:00 |
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Stephen Twigg
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e90f2484aa
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Sync with riscv-opcodes (csr register mapping)
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2014-04-08 15:48:37 -07:00 |
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Andrew Waterman
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54cbf0c4f1
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Add (unused) RV32 CSRs
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2014-03-15 17:33:17 -07:00 |
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Andrew Waterman
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a0389645b7
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New FP encoding; improved FP implementation
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2014-03-11 18:58:24 -07:00 |
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Andrew Waterman
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00bc1a2293
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Add fclass.{s|d} instructions
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2014-03-10 16:59:24 -07:00 |
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Andrew Waterman
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8e3ca609f7
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Renumber uarch CSRs into custom CSR space
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2014-02-14 17:40:00 -08:00 |
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Andrew Waterman
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e7a726fbac
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Make uarch counters read-only
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2014-02-06 01:48:56 -08:00 |
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Andrew Waterman
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62e9313aef
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Add 16 microarchitectural counters
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2014-02-06 00:13:02 -08:00 |
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Andrew Waterman
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6ba2c1abe5
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Use auto-generated CAUSE constants
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2014-01-21 15:01:54 -08:00 |
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Andrew Waterman
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c546f66404
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Swap JAL/JALR encodings (again)
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2014-01-13 00:54:49 -08:00 |
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Andrew Waterman
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da3135ac9b
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Begin integer unit clean-up
...to make it easier to generate the superscalar version of the core.
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2013-12-09 15:06:13 -08:00 |
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Andrew Waterman
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924261e2b2
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Update to new privileged ISA... phew
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2013-11-25 04:35:15 -08:00 |
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Yunsup Lee
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68e270eeb2
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fix slli/slliw encoding bug
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2013-11-21 14:44:58 -08:00 |
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Andrew Waterman
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1d2f4f8437
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New ISA encoding, AUIPC semantics
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2013-09-21 06:32:40 -07:00 |
|
Andrew Waterman
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25ab402932
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swap JAL, JALR encodings
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2013-09-15 04:29:06 -07:00 |
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Andrew Waterman
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88d1c47665
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don't disassemble within chisel
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2013-09-15 04:14:45 -07:00 |
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Andrew Waterman
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d053bdc89f
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Remove Hwacha from Rocket
Soon it will use the coprocessor interface.
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2013-09-12 22:34:38 -07:00 |
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Andrew Waterman
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243c4ae342
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sync up rocket with new isa
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2013-09-12 03:44:38 -07:00 |
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Andrew Waterman
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d4a0db4575
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Reflect ISA changes
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2013-08-24 14:43:55 -07:00 |
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Henry Cook
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1a9e43aa11
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initial attempt at upgrade
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2013-08-12 10:39:11 -07:00 |
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Henry Cook
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9abdf4e154
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Make compatible with scala 2.10. List.sort deprecated. Refactor constants into package object.
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2013-07-23 20:27:58 -07:00 |
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Andrew Waterman
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95c5147dc5
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Add RISC-V instruction disassembler
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2013-06-13 10:31:04 -07:00 |
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Andrew Waterman
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50ccc20bf3
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replace RDNPC with AUIPC
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2013-04-22 04:20:15 -07:00 |
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Andrew Waterman
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8cbdeb2abf
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add LR/SC support
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2013-04-04 17:07:09 -07:00 |
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Henry Cook
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dfdfddebe8
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constants as traits
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2012-10-07 22:20:03 -07:00 |
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Andrew Waterman
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e0e1cd5d32
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add IPIs and an IPI test
IPIs are routed through the HTIF, which seems weird, but that makes it
so cores can bring each other out of reset with IPIs.
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2012-05-08 22:58:00 -07:00 |
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Andrew Waterman
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54fa6f660d
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new supervisor mode
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2012-03-24 13:03:31 -07:00 |
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Yunsup Lee
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aaed0241af
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get rid of vxcptwait
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2012-03-21 15:09:04 -07:00 |
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Andrew Waterman
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c4a91303fb
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update vector fence names and encoding
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2012-03-18 20:42:38 -07:00 |
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Yunsup Lee
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98e10ddc3c
|
update vector exception instructions
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2012-03-18 16:36:12 -07:00 |
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Yunsup Lee
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040d62f372
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refactored vector exception handling interface
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2012-03-13 23:45:34 -07:00 |
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Yunsup Lee
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5655dbd5da
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add vvcfg and vtcfg instructions
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2012-03-13 23:45:34 -07:00 |
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Yunsup Lee
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44ff22a26f
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vector exception handler now handles prefetches correctly
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2012-03-10 12:54:36 -08:00 |
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Yunsup Lee
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e28a551368
|
refactor code related to vector exceptions
- revisied interfaces
- new instructions
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2012-03-03 15:15:00 -08:00 |
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Yunsup Lee
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94ba32bbd3
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change package name and sbt project name to rocket
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2012-02-25 17:09:26 -08:00 |
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Yunsup Lee
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0ea2704b80
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new mftx instruction format
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2011-12-12 03:23:12 -08:00 |
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Rimas Avizienis
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fc0f20643a
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cleanup
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2011-11-15 18:06:41 -08:00 |
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Rimas Avizienis
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7b3c34a341
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regenerated instruction encodings using parse-opcodes
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2011-11-13 00:59:02 -08:00 |
|
Rimas Avizienis
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c06e2d16e4
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initial commit of rocket chisel project, riscv assembly tests and benchmarks
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2011-10-25 23:02:47 -07:00 |
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