308 lines
15 KiB
Scala
308 lines
15 KiB
Scala
package rocket
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import Chisel._
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import Node._
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/* Automatically generated by parse-opcodes */
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object Instructions {
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def BEQ = Bits("b?????????????????000?????1100011")
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def BNE = Bits("b?????????????????001?????1100011")
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def BLT = Bits("b?????????????????100?????1100011")
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def BGE = Bits("b?????????????????101?????1100011")
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def BLTU = Bits("b?????????????????110?????1100011")
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def BGEU = Bits("b?????????????????111?????1100011")
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def JALR = Bits("b?????????????????000?????1100111")
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def JAL = Bits("b?????????????????????????1101111")
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def LUI = Bits("b?????????????????????????0110111")
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def AUIPC = Bits("b?????????????????????????0010111")
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def ADDI = Bits("b?????????????????000?????0010011")
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def SLLI = Bits("b000000???????????001?????0010011")
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def SLTI = Bits("b?????????????????010?????0010011")
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def SLTIU = Bits("b?????????????????011?????0010011")
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def XORI = Bits("b?????????????????100?????0010011")
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def SRLI = Bits("b000000???????????101?????0010011")
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def SRAI = Bits("b010000???????????101?????0010011")
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def ORI = Bits("b?????????????????110?????0010011")
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def ANDI = Bits("b?????????????????111?????0010011")
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def ADD = Bits("b0000000??????????000?????0110011")
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def SUB = Bits("b0100000??????????000?????0110011")
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def SLL = Bits("b0000000??????????001?????0110011")
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def SLT = Bits("b0000000??????????010?????0110011")
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def SLTU = Bits("b0000000??????????011?????0110011")
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def XOR = Bits("b0000000??????????100?????0110011")
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def SRL = Bits("b0000000??????????101?????0110011")
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def SRA = Bits("b0100000??????????101?????0110011")
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def OR = Bits("b0000000??????????110?????0110011")
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def AND = Bits("b0000000??????????111?????0110011")
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def ADDIW = Bits("b?????????????????000?????0011011")
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def SLLIW = Bits("b0000000??????????001?????0011011")
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def SRLIW = Bits("b0000000??????????101?????0011011")
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def SRAIW = Bits("b0100000??????????101?????0011011")
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def ADDW = Bits("b0000000??????????000?????0111011")
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def SUBW = Bits("b0100000??????????000?????0111011")
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def SLLW = Bits("b0000000??????????001?????0111011")
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def SRLW = Bits("b0000000??????????101?????0111011")
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def SRAW = Bits("b0100000??????????101?????0111011")
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def LB = Bits("b?????????????????000?????0000011")
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def LH = Bits("b?????????????????001?????0000011")
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def LW = Bits("b?????????????????010?????0000011")
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def LD = Bits("b?????????????????011?????0000011")
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def LBU = Bits("b?????????????????100?????0000011")
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def LHU = Bits("b?????????????????101?????0000011")
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def LWU = Bits("b?????????????????110?????0000011")
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def SB = Bits("b?????????????????000?????0100011")
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def SH = Bits("b?????????????????001?????0100011")
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def SW = Bits("b?????????????????010?????0100011")
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def SD = Bits("b?????????????????011?????0100011")
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def FENCE = Bits("b?????????????????000?????0001111")
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def FENCE_I = Bits("b?????????????????001?????0001111")
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def MUL = Bits("b0000001??????????000?????0110011")
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def MULH = Bits("b0000001??????????001?????0110011")
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def MULHSU = Bits("b0000001??????????010?????0110011")
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def MULHU = Bits("b0000001??????????011?????0110011")
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def DIV = Bits("b0000001??????????100?????0110011")
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def DIVU = Bits("b0000001??????????101?????0110011")
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def REM = Bits("b0000001??????????110?????0110011")
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def REMU = Bits("b0000001??????????111?????0110011")
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def MULW = Bits("b0000001??????????000?????0111011")
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def DIVW = Bits("b0000001??????????100?????0111011")
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def DIVUW = Bits("b0000001??????????101?????0111011")
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def REMW = Bits("b0000001??????????110?????0111011")
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def REMUW = Bits("b0000001??????????111?????0111011")
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def AMOADD_W = Bits("b00000????????????010?????0101111")
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def AMOXOR_W = Bits("b00100????????????010?????0101111")
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def AMOOR_W = Bits("b01000????????????010?????0101111")
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def AMOAND_W = Bits("b01100????????????010?????0101111")
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def AMOMIN_W = Bits("b10000????????????010?????0101111")
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def AMOMAX_W = Bits("b10100????????????010?????0101111")
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def AMOMINU_W = Bits("b11000????????????010?????0101111")
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def AMOMAXU_W = Bits("b11100????????????010?????0101111")
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def AMOSWAP_W = Bits("b00001????????????010?????0101111")
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def LR_W = Bits("b00010??00000?????010?????0101111")
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def SC_W = Bits("b00011????????????010?????0101111")
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def AMOADD_D = Bits("b00000????????????011?????0101111")
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def AMOXOR_D = Bits("b00100????????????011?????0101111")
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def AMOOR_D = Bits("b01000????????????011?????0101111")
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def AMOAND_D = Bits("b01100????????????011?????0101111")
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def AMOMIN_D = Bits("b10000????????????011?????0101111")
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def AMOMAX_D = Bits("b10100????????????011?????0101111")
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def AMOMINU_D = Bits("b11000????????????011?????0101111")
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def AMOMAXU_D = Bits("b11100????????????011?????0101111")
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def AMOSWAP_D = Bits("b00001????????????011?????0101111")
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def LR_D = Bits("b00010??00000?????011?????0101111")
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def SC_D = Bits("b00011????????????011?????0101111")
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def SCALL = Bits("b00000000000000000000000001110011")
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def SBREAK = Bits("b00000000000100000000000001110011")
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def SRET = Bits("b10000000000000000000000001110011")
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def CSRRW = Bits("b?????????????????001?????1110011")
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def CSRRS = Bits("b?????????????????010?????1110011")
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def CSRRC = Bits("b?????????????????011?????1110011")
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def CSRRWI = Bits("b?????????????????101?????1110011")
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def CSRRSI = Bits("b?????????????????110?????1110011")
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def CSRRCI = Bits("b?????????????????111?????1110011")
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def FADD_S = Bits("b0000000??????????????????1010011")
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def FSUB_S = Bits("b0000100??????????????????1010011")
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def FMUL_S = Bits("b0001000??????????????????1010011")
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def FDIV_S = Bits("b0001100??????????????????1010011")
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def FSQRT_S = Bits("b001000000000?????????????1010011")
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def FSGNJ_S = Bits("b0010100??????????000?????1010011")
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def FSGNJN_S = Bits("b0011000??????????000?????1010011")
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def FSGNJX_S = Bits("b0011100??????????000?????1010011")
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def FADD_D = Bits("b0000001??????????????????1010011")
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def FSUB_D = Bits("b0000101??????????????????1010011")
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def FMUL_D = Bits("b0001001??????????????????1010011")
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def FDIV_D = Bits("b0001101??????????????????1010011")
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def FSQRT_D = Bits("b001000100000?????????????1010011")
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def FSGNJ_D = Bits("b0010101??????????000?????1010011")
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def FSGNJN_D = Bits("b0011001??????????000?????1010011")
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def FSGNJX_D = Bits("b0011101??????????000?????1010011")
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def FCVT_L_S = Bits("b010000000000?????????????1010011")
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def FCVT_LU_S = Bits("b010010000000?????????????1010011")
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def FCVT_W_S = Bits("b010100000000?????????????1010011")
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def FCVT_WU_S = Bits("b010110000000?????????????1010011")
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def FCVT_L_D = Bits("b010000100000?????????????1010011")
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def FCVT_LU_D = Bits("b010010100000?????????????1010011")
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def FCVT_W_D = Bits("b010100100000?????????????1010011")
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def FCVT_WU_D = Bits("b010110100000?????????????1010011")
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def FCVT_S_L = Bits("b011000000000?????????????1010011")
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def FCVT_S_LU = Bits("b011010000000?????????????1010011")
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def FCVT_S_W = Bits("b011100000000?????????????1010011")
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def FCVT_S_WU = Bits("b011110000000?????????????1010011")
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def FCVT_D_L = Bits("b011000100000?????????????1010011")
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def FCVT_D_LU = Bits("b011010100000?????????????1010011")
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def FCVT_D_W = Bits("b011100100000?????????????1010011")
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def FCVT_D_WU = Bits("b011110100000?????????????1010011")
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def FCVT_S_D = Bits("b100010000000?????????????1010011")
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def FCVT_D_S = Bits("b100000100000?????????????1010011")
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def FEQ_S = Bits("b1010100??????????000?????1010011")
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def FLT_S = Bits("b1011000??????????000?????1010011")
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def FLE_S = Bits("b1011100??????????000?????1010011")
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def FEQ_D = Bits("b1010101??????????000?????1010011")
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def FLT_D = Bits("b1011001??????????000?????1010011")
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def FLE_D = Bits("b1011101??????????000?????1010011")
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def FMIN_S = Bits("b1100000??????????000?????1010011")
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def FMAX_S = Bits("b1100100??????????000?????1010011")
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def FMIN_D = Bits("b1100001??????????000?????1010011")
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def FMAX_D = Bits("b1100101??????????000?????1010011")
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def FMV_X_S = Bits("b111000000000?????000?????1010011")
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def FMV_X_D = Bits("b111000100000?????000?????1010011")
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def FMV_S_X = Bits("b111100000000?????000?????1010011")
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def FMV_D_X = Bits("b111100100000?????000?????1010011")
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def FLW = Bits("b?????????????????010?????0000111")
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def FLD = Bits("b?????????????????011?????0000111")
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def FSW = Bits("b?????????????????010?????0100111")
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def FSD = Bits("b?????????????????011?????0100111")
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def FMADD_S = Bits("b?????00??????????????????1000011")
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def FMSUB_S = Bits("b?????00??????????????????1000111")
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def FNMSUB_S = Bits("b?????00??????????????????1001011")
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def FNMADD_S = Bits("b?????00??????????????????1001111")
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def FMADD_D = Bits("b?????01??????????????????1000011")
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def FMSUB_D = Bits("b?????01??????????????????1000111")
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def FNMSUB_D = Bits("b?????01??????????????????1001011")
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def FNMADD_D = Bits("b?????01??????????????????1001111")
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def CUSTOM0 = Bits("b?????????????????000?????0001011")
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def CUSTOM0_RS1 = Bits("b?????????????????010?????0001011")
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def CUSTOM0_RS1_RS2 = Bits("b?????????????????011?????0001011")
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def CUSTOM0_RD = Bits("b?????????????????100?????0001011")
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def CUSTOM0_RD_RS1 = Bits("b?????????????????110?????0001011")
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def CUSTOM0_RD_RS1_RS2 = Bits("b?????????????????111?????0001011")
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def CUSTOM1 = Bits("b?????????????????000?????0101011")
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def CUSTOM1_RS1 = Bits("b?????????????????010?????0101011")
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def CUSTOM1_RS1_RS2 = Bits("b?????????????????011?????0101011")
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def CUSTOM1_RD = Bits("b?????????????????100?????0101011")
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def CUSTOM1_RD_RS1 = Bits("b?????????????????110?????0101011")
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def CUSTOM1_RD_RS1_RS2 = Bits("b?????????????????111?????0101011")
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def CUSTOM2 = Bits("b?????????????????000?????1011011")
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def CUSTOM2_RS1 = Bits("b?????????????????010?????1011011")
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def CUSTOM2_RS1_RS2 = Bits("b?????????????????011?????1011011")
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def CUSTOM2_RD = Bits("b?????????????????100?????1011011")
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def CUSTOM2_RD_RS1 = Bits("b?????????????????110?????1011011")
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def CUSTOM2_RD_RS1_RS2 = Bits("b?????????????????111?????1011011")
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def CUSTOM3 = Bits("b?????????????????000?????1111011")
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def CUSTOM3_RS1 = Bits("b?????????????????010?????1111011")
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def CUSTOM3_RS1_RS2 = Bits("b?????????????????011?????1111011")
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def CUSTOM3_RD = Bits("b?????????????????100?????1111011")
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def CUSTOM3_RD_RS1 = Bits("b?????????????????110?????1111011")
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def CUSTOM3_RD_RS1_RS2 = Bits("b?????????????????111?????1111011")
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}
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object Causes {
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val misaligned_fetch = 0x0
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val fault_fetch = 0x1
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val illegal_instruction = 0x2
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val privileged_instruction = 0x3
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val fp_disabled = 0x4
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val syscall = 0x6
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val breakpoint = 0x7
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val misaligned_load = 0x8
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val misaligned_store = 0x9
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val fault_load = 0xa
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val fault_store = 0xb
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val accelerator_disabled = 0xc
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val all = {
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val res = collection.mutable.ArrayBuffer[Int]()
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res += misaligned_fetch
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res += fault_fetch
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res += illegal_instruction
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res += privileged_instruction
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res += fp_disabled
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res += syscall
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res += breakpoint
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res += misaligned_load
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res += misaligned_store
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res += fault_load
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res += fault_store
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res += accelerator_disabled
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res.toArray
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}
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}
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object CSRs {
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val fflags = 0x1
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val frm = 0x2
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val fcsr = 0x3
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val sup0 = 0x500
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val sup1 = 0x501
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val epc = 0x502
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val badvaddr = 0x503
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val ptbr = 0x504
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val asid = 0x505
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val count = 0x506
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val compare = 0x507
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val evec = 0x508
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val cause = 0x509
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val status = 0x50a
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val hartid = 0x50b
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val impl = 0x50c
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val fatc = 0x50d
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val send_ipi = 0x50e
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val clear_ipi = 0x50f
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val stats = 0x51c
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val reset = 0x51d
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val tohost = 0x51e
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val fromhost = 0x51f
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val cycle = 0xc00
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val time = 0xc01
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val instret = 0xc02
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val uarch0 = 0xcc0
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val uarch1 = 0xcc1
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val uarch2 = 0xcc2
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val uarch3 = 0xcc3
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val uarch4 = 0xcc4
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val uarch5 = 0xcc5
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val uarch6 = 0xcc6
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val uarch7 = 0xcc7
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val uarch8 = 0xcc8
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val uarch9 = 0xcc9
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val uarch10 = 0xcca
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val uarch11 = 0xccb
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val uarch12 = 0xccc
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val uarch13 = 0xccd
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val uarch14 = 0xcce
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val uarch15 = 0xccf
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val all = {
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val res = collection.mutable.ArrayBuffer[Int]()
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res += fflags
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res += frm
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res += fcsr
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res += sup0
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res += sup1
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res += epc
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res += badvaddr
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res += ptbr
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res += asid
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res += count
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res += compare
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res += evec
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res += cause
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res += status
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res += hartid
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res += impl
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res += fatc
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res += send_ipi
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res += clear_ipi
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res += stats
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res += reset
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res += tohost
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res += fromhost
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res += cycle
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res += time
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res += instret
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res += uarch0
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res += uarch1
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res += uarch2
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res += uarch3
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res += uarch4
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res += uarch5
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res += uarch6
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res += uarch7
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res += uarch8
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res += uarch9
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res += uarch10
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res += uarch11
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res += uarch12
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res += uarch13
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res += uarch14
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res += uarch15
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res.toArray
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}
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}
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