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Commit Graph

978 Commits

Author SHA1 Message Date
Howard Mao
1db2da00f3 Merge branch 'master' into rocc-fpu-port 2015-11-30 19:18:58 -08:00
Howard Mao
e80340198a use implicit parameters for ALU 2015-11-30 17:35:33 -08:00
Howard Mao
9256239206 implement support for multiple RoCC accelerators 2015-11-26 12:46:01 -08:00
Howard Mao
58b0a86834 some modifications to AccumulatorExample 2015-11-26 08:48:19 -08:00
Andrew Waterman
e203b8b378 Make ALU generic for zscale 2015-11-24 19:17:07 -08:00
Andrew Waterman
5294e94794 Remove CSR back pressure ability
We were using it for IPIs, but no longer need it.
2015-11-24 18:28:14 -08:00
Andrew Waterman
4616db4695 Make RegFile/ImmGen usable by zscale 2015-11-24 18:27:07 -08:00
Andrew Waterman
6d1bf5c014 Use generic LoadGen/StoreGen 2015-11-24 18:13:33 -08:00
Sagar Karandikar
65632c875a Merge branch 'master' into rocc-fpu-port 2015-11-21 02:24:38 -08:00
Howard Mao
b0a06a77db fix a few Chisel3 compat issues 2015-11-20 13:33:15 -08:00
Yunsup Lee
94d2dd3053 Merge remote-tracking branch 'origin/master' into rocc-fpu-port 2015-11-16 23:29:25 -08:00
Andrew Waterman
0f092b9b59 Remove IPI network
This is now provided via MMIO.
2015-11-16 21:51:43 -08:00
Yunsup Lee
5e2698adbc Merge remote-tracking branch 'origin/master' into rocc-fpu-port 2015-11-14 16:44:55 -08:00
Yunsup Lee
213c1a4c81 fix fdiv/fsqrt control bug in fpu 2015-11-14 16:43:15 -08:00
Yunsup Lee
4dd097d156 Merge remote-tracking branch 'origin/master' into rocc-fpu-port 2015-11-14 14:52:13 -08:00
Yunsup Lee
3c3c946755 move to new version of hardfloat 2015-11-14 14:49:17 -08:00
Yunsup Lee
608e4b2851 Merge remote-tracking branch 'origin/master' into rocc-fpu-port 2015-11-12 20:44:25 -08:00
Howard Mao
19daee10f0 use default constructors for IOMSHR acquire construction 2015-11-12 15:54:05 -08:00
jackkoenig
1e259a55da Fix SimpleHellaCacheIF assumption about receiving rejected request back 2 cycles later 2015-11-08 21:16:31 -08:00
Yunsup Lee
df5daaa72e Merge remote-tracking branch 'origin/master' into rocc-fpu-port 2015-11-06 23:57:42 -08:00
Andrew Waterman
2f515b2af6 Reduce critical path for fdiv valid signal 2015-11-06 23:28:31 -08:00
Colin Schmidt
86d67051b2 Merge commit 'e31be75' into rocc-fpu-port 2015-10-26 16:29:51 -07:00
Yunsup Lee
c7235fecb5 further state optimization in CSRfile when not UseVM 2015-10-25 10:23:46 -07:00
Colin Schmidt
652fb393a3 Merge remote-tracking branch 'origin/master' into rocc-fpu-port 2015-10-22 16:38:28 -07:00
Jim Lawson
0c587704a7 Add ability to generate libraryDependency on cde. 2015-10-22 11:37:20 -07:00
Henry Cook
4f8468b60f depend on external cde library 2015-10-21 18:19:23 -07:00
Colin Schmidt
942f6a7d7f Merge commit 'd1eae61970f864afe4fde8ca7f75380c70c4658f' into rocc-fpu-port 2015-10-21 17:18:20 -07:00
Colin Schmidt
97f29b1618 Merge remote-tracking branch 'origin/master' into rocc-fpu-port 2015-10-21 11:33:42 -07:00
Howard Mao
0b7c828b5d go back to using standard LockingArbiter 2015-10-21 09:15:51 -07:00
Howard Mao
c68d9f8137 make ProbeUnit state machine easier to understand 2015-10-20 23:25:23 -07:00
Henry Cook
1a1185be3f Vectorize ROCC and Tile memory interfaces 2015-10-20 15:02:24 -07:00
Colin Schmidt
2cee8c8bec Merge commit '3c3e35a56e954b35e6ceb17179ebadc52e8d9b3f' into rocc-fpu-port 2015-10-18 13:09:17 -07:00
Henry Cook
6f8997bee9 Minor refactor of StoreGen/AMOALU. 2015-10-16 19:12:46 -07:00
Henry Cook
1441590c3b add enabled field to BTBParameters 2015-10-16 19:12:39 -07:00
Henry Cook
969ecaecf8 pass parameters to BuildRoCC 2015-10-14 14:16:47 -07:00
Henry Cook
68cb54bc68 refactor tilelink params 2015-10-14 12:14:36 -07:00
Henry Cook
4508666d96 log2ceil 2015-10-06 18:22:47 -07:00
Henry Cook
8173695800 added HasAddrMapParameters 2015-10-06 18:22:40 -07:00
Henry Cook
84576650b5 Removed all traces of params 2015-10-05 21:48:05 -07:00
Henry Cook
69a4dd0a79 refactor NASTI to not use param 2015-10-02 14:20:47 -07:00
Howard Mao
19656e4abe make sure to generate release from clean coh state on probe miss 2015-09-30 16:58:18 -07:00
Andrew Waterman
833909a2b5 Chisel3 compatibility fixes 2015-09-30 14:36:26 -07:00
Andrew Waterman
a7c908cb83 Don't declare Reg inside of when
We haven't yet decided what the Chisel3 semantics for this will be.
2015-09-30 12:43:36 -07:00
Howard Mao
2f3d15675c fix DataArray writemask in L1D 2015-09-28 16:02:39 -07:00
Andrew Waterman
f8a7a80644 Make perf counters optional 2015-09-28 13:55:23 -07:00
Andrew Waterman
5e88ead984 Add pseudo-ops to instructions.scala 2015-09-28 11:52:27 -07:00
Andrew Waterman
b93a94597c Remove needless control logic 2015-09-27 13:31:52 -07:00
Howard Mao
4bda6b6757 fix bug in tlb refill 2015-09-26 21:27:36 -07:00
Howard Mao
6bf8f41cef make sure passthrough requests are treated as vm_enabled = false 2015-09-26 20:29:51 -07:00
Andrew Waterman
c3fff12ff0 Revert "replace remaining uses of Vec.fill"
This reverts commit f7a0d125e83f8ca59d9913bb1db79cef5a6d344a.
2015-09-25 17:09:06 -07:00