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Commit Graph

74 Commits

Author SHA1 Message Date
Megan Wachs
dd4a50c452 Add JTAG DTM and test support in simulation
Initial cut

checkpoint which compiles and runs but there is some off-by-1 in the protocol

Debugging the clock crossing logic

checkpoint which works

Clean up the AsyncMailbox black box
2016-08-19 16:08:17 -07:00
Andrew Waterman
ed827678ac Write test harness in Chisel
This is an unavoidably invasive commit, because it affects the unit tests
(which formerly exited using stop()), the test harness Verilog generator
(since it is no longer necessary), and the DRAM model (since it is no
longer connected).  However, this should substantially reduce the effort
of building test harnesses in the future, since manual or semi-automatic
Verilog writing should no longer be necessary.  Furthermore, there is now
very little duplication of effort between the Verilator and VCS test
harnesses.

This commit removes support for DRAMsim, which is a bit of an unfortunate
consequence.  The main blocker is the lack of Verilog parameterization for
BlackBox.  It would be straightforward to revive DRAMsim once support for
that feature is added to Chisel and FIRRTL.  But that might not even be
necessary, as we move towards synthesizable DRAM models and FAME-1
transformations.
2016-08-15 23:27:27 -07:00
Andrew Waterman
87a4858aa6 Exit from testbench, not C code
Otherwise, we don't get coverage data from the simulator.
2016-06-23 20:54:07 -07:00
Andrew Waterman
30331fcaeb Remove HTIF; use debug module for testing in simulation 2016-06-23 00:32:05 -07:00
Howard Mao
9b9ddd0d54 get rid of leftover backup memory code 2016-06-22 16:06:41 -07:00
Howard Mao
82169e971e Dynamically compute number of L1 client channels
Until now, the number of L1 client channels was set statically in the
configuration. This static configuration also assumed the same number of
cached and uncached channels per tile. As we plan to move towards
heterogenous multicore systems, this restriction should be removed.

This commit changes the generator so that number of channels per tile
can be independently set (using cde.Parameters.alterPartial).
The OuterMemorySystem will dynamically compute the number of cached and
uncached channels by summing the number of each kind of channel per core.
2016-06-20 13:02:31 -07:00
Howard Mao
a809a1712a make sure clocks and reset signals get intialized properly 2016-06-08 15:38:39 -07:00
Howard Mao
f52fc655a5 remove zscale 2016-05-19 09:43:15 -07:00
Andrew Waterman
1f211b37df WIP on new memory map 2016-04-27 14:57:54 -07:00
Andrew Waterman
46d7dceb1e Disable printf/assert during reset 2016-04-01 18:18:08 -07:00
Palmer Dabbelt
a0f3189c74 Change MIF_DATA_BITS back to 64
It turns out the Chisel C++ backend can't emit correct initialization
code for a 128 bit wide NastiROM.  Rather than trying to fix Chisel, I'm
just going to hack up the backup memory port Verilog harness a bit more
to make it work.

Note that the backup memory port Verilog already couldn't take arbitrary
parameters for MIF_*, so it's not like we're losing any flexibility
here.
2016-02-27 11:43:44 -08:00
Palmer Dabbelt
7c0c48fac4 Resurrect the backup memory port
We need this to work for our chip, and it's not been tested in a long
time in upstream -- it didn't even used to build since the Nasti
conversion.  This makes a few changes:

 * Rather than calling the backup memory port parameters MEM_*, it calls
   them MIF_* (to match the MIT* paramater objects).  A new name was
   necessary because the Nasti stuff is now dumped as MEM_*, which has
   similar names but incompatible values.

 * p(MIFDataBits) was changed back to 128, as otherwise the backup
   memory port doesn't work (it only send half a TileLink transaction).
   64 also causes readmemh to bail out, but changing the elf2hex parameters
   works around that.

 * A configuration was added that enabled the backup memory port in the
   tester.  While this is kind of an awkward way to do it, I want to
   make sure I can start testing this regularly and this makes it easy to
   integrate.
2016-02-27 10:46:56 -08:00
Andrew Waterman
5195a5b891 Remove IPI network
This is now provided via MMIO.
2015-11-16 21:53:14 -08:00
Howard Mao
bbf14ddc01 use definitions in consts header whenever possible 2015-11-05 10:48:32 -08:00
Yunsup Lee
0d245741bc add multichannel NASTI support in Verilog testbench 2015-11-05 10:48:32 -08:00
Howard Mao
9dabcab9c2 Get rid of MemIO in Top and replace with AXI throughout 2015-11-05 10:48:32 -08:00
Yunsup Lee
a175afae73 make ZscaleChip work with new parameters framework 2015-10-25 10:24:39 -07:00
Howard Mao
4346111d2a fix remaining vsim harness typo 2015-10-19 20:20:14 -07:00
Yunsup Lee
e7802825c3 add Zscale testing 2015-07-17 12:02:02 -07:00
Henry Cook
d3ccec1044 Massive update containing several months of changes from the now-defunct private chip repo.
* Adds support for a L2 cache with directory bits for tracking L1 coherence (DefaultL2Config), and new metadata-based coherence API.
* Additional tests.
* New virtual memory implementation, priviliged architecture (1.7), custom CSRs, FDivSqrt unit
* Updated TileLink protocol, NASTI protocol SHIMs.
* Lays groundwork for multiple top-level memory channels, superscalar fetch.
* Bump all submodules.
2015-07-02 14:43:30 -07:00
Yunsup Lee
1cfd9f5a0e add LICENSE 2014-09-12 10:15:04 -07:00
Yunsup Lee
02c08a156f generate consts.vh from chisel source 2014-09-10 17:14:55 -07:00
Yunsup Lee
ddfd3ce968 further generalize fpga/vlsi builds 2014-09-08 00:21:57 -07:00
Yunsup Lee
c03c09ec31 update for rocket-chip release 2014-08-31 20:26:55 -07:00